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cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 002-00247 rev. *g revised october 27, 2016 s29gl01gt, s29gl512t 1 gbit (128 mbyte), 512 mbit (64 mbyte) gl-t mirrorbit ? eclipse? flash general description the cypress ? s29gl01gt/512t are mirrorbit ? eclipse? flash products fabricated on 45 nm process technology. these devices offer a fast page access time as fast as 15 ns, with a corresponding random access time as fast as 100 ns. they feature a write buffer that allows a maximum of 256 words/512 bytes to be progra mmed in one operation, resulting in faster effective programmin g time than standard programming al gorithms. this makes these devices ideal for to day?s embedded applications that require higher density, better performance, and lower power consumption. distinctive characteristics ? 45 nm mirrorbit eclipse technology ? single supply (v cc ) for read / program / erase (2.7 v to 3.6 v) ? versatile i/o feature ? wide i/o voltage range (v io ): 1.65 v to v cc ? x8/x16 data bus ? asynchronous 32-byte page read ? 512-byte programming buffer ? programming in page multiples, up to a maximum of 512 bytes ? single word and multiple program on same word options ? automatic error checking and correction (ecc) ? internal hardware ecc with single bit error correction ? sector erase ? uniform 128-kbyte sectors ? suspend and resume commands for program and erase operations ? status register, data polling, and ready/busy pin methods to determine device status ? advanced sector protection (asp) ? volatile and non-volatile protection methods for each sector ? separate 2048-byte one time program (otp) array ? four lockable regions (ssr0 - ssr3) ? ssr0 is factory locked ? ssr3 is password read protect ? common flash interface (cfi) parameter table ? temperature range / grade: ? industrial ( ? 40 c to +85 c) ? industrial plus ( ? 40 c to +105 c) ? extended ( ? 40 c to +125 c) ? automotive, aec-q100 grade 3 (?40 c to +85 c) ? automotive, aec-q100 grade 2 (?40 c to +105 c) ? 100,000 program / erase cycles ? 20-year data retention ? packaging options ? 56-pin tsop ? 64-ball laa fortified bga, 13 mm ? 11 mm ? 64-ball lae fortified bga, 9 mm ? 9 mm ? 56-ball vbu fortified bga, 9 mm ? 7 mm
document number: 002-00247 rev. *g page 2 of 105 s29gl01gt, s29gl512t performance summary performance summary for operating temperature range of ? 40 c to +85 c performance summary operating temperature range of ?? 40 c to +105 c performance summary operating temperature range of ? 40 c to +125 c typical program and erase rates maximum current consumption maximum read access times density voltage range random access time (t acc ) page access time (t pacc ) ce# access time (t ce ) oe# access time (t oe ) 512 mb full v cc = v io 100 15 100 25 versatile i/o v io 110 25 110 35 1 gb full v cc = v io 100 15 100 25 versatile i/o v io 110 25 110 35 maximum read access times density voltage range random access time (t acc ) page access time (t pacc ) ce# access time (t ce ) oe# access time (t oe ) 512 mb full v cc = v io 110 15 110 25 versatile i/o v io 120 25 120 35 1 gb full v cc = v io 110 15 110 25 versatile i/o v io 120 25 120 35 maximum read access times density voltage range random access time (t acc ) page access time (t pacc ) ce# access time (t ce ) oe# access time (t oe ) 512 mb full v cc = v io 120 15 120 25 versatile i/o v io 130 25 130 35 1 gb full v cc = v io 120 15 120 25 versatile i/o v io 130 25 130 35 operation ? 40 c to +85 c ? 40 c to +105 c ? 40 c to +125 c buffer programming (512 bytes) 1.14 mb/s 1.14 mb/s 1.14 mb/s sector erase (128 kbytes) 245 kb/s 245 kb/s 245 kb/s operation ? 40 c to +85 c ? 40 c to +105 c ? 40 c to +125 c active read at 5 mhz, 30 pf 60 ma 60 ma 60 ma program 100 ma 100 ma 100 ma erase 100 ma 100 ma 100 ma standby 100 a 200 a 215 a
s29gl01gt, s29gl512t document number: 002-00247 rev. *g page 3 of 105 contents 1. product overview ....................................................... 4 software interface 2. address space overlays ............................................ 6 2.1 flash memory array...................................................... 7 2.2 device id and cfi (id-cfi) aso .................................. 8 2.3 status register aso..................................................... 9 2.4 data polling status aso............................................... 9 2.5 secure silicon re gion aso .......................................... 9 2.6 sector protection control... ......................................... 10 2.7 ecc status aso......................................................... 11 3. data protection ......................................................... 12 3.1 device protection methods ......................................... 12 3.2 command protection .................................................. 12 3.3 secure silicon region (otp) ...................................... 12 3.4 sector protection methods.......................................... 13 4. read operations ....................................................... 18 4.1 asynchronous read.................................................... 18 4.2 page mode read ........................................................ 18 5. embedded operations .............................................. 19 5.1 embedded algorithm controlle r (eac) ........ ............... 19 5.2 program and erase summary .................................... 19 5.3 automatic ecc ........................................................... 21 5.4 command set ............................................................. 22 5.5 status monitoring ........................................................ 36 5.6 error types and clearing procedures ........................ 41 5.7 embedded algorithm perform ance table...... ............. 44 6. data integrity ............................................................. 47 6.1 erase endurance ........................................................ 47 6.2 data retention .. .......................................................... 47 7. software interface reference .................................. 48 7.1 command summary ................................................... 48 7.2 device id and common fl ash interface (id-cfi) aso map ............................................................................ 55 hardware interface 8. signal descriptions .................................................. 60 8.1 address and data configuration................................. 60 8.2 input/output summary................................................ 60 8.3 word/byte configuration............................................. 61 8.4 versatile i/o feature.................................................... 61 8.5 ready/busy# (ry/by#) ............................................... 61 8.6 hardware reset ........................................................... 61 9. signal protocols ......................................................... 62 9.1 interface states............................................................ 62 9.2 power-off with hardware data protection ................... 63 9.3 power conservation modes... ...................................... 63 9.4 read ............................................................................ 63 9.5 write ............................................................................ 64 10. electrical specifications ............................................ 65 10.1 absolute maximum ratings .. ....................................... 65 10.2 thermal resistance ..................................................... 65 10.3 latchup characteristics ............................................... 65 10.4 operating ranges........................................................ 66 10.5 dc characteristics ....................................................... 68 10.6 capacitance characteristics ........................................ 71 11. timing specifications ................................................ 72 11.1 key to switching waveforms ....................................... 72 11.2 ac test conditions ........... ........................................... 72 11.3 power-on reset (por) an d warm reset ................... 73 11.4 ac characteristics ....................................................... 75 12. physical interface ...................................................... 90 12.1 56-pin tsop................................................................ 90 12.2 64-ball fbga ............................................................... 92 12.3 56-ball fbga ............................................................... 95 13. special handling instructions for fbga package .. 96 14. ordering information ................................................. 97 15. other resources ...................................................... 101 15.1 cypress flash memory road map ............................. 101 15.2 links to software ................. ...................................... 101 15.3 links to application notes.... ...................................... 101 16. document history page .......................................... 102 sales, solutions, and legal information .........................105 worldwide sales and design supp ort ............ ............. 105 products ...................................................................... 105 psoc? solutions ........................................................ 105 cypress developer community ................................... 105 technical support ................. ...................................... 105
document number: 002-00247 rev. *g page 4 of 105 s29gl01gt, s29gl512t 1. product overview the gl-t family consists of 512-mbit to 1-gbit, 3.0 v core, ve rsatile i/o, non-volatile, flash me mory devices. these devices ha ve an 8-bit (byte) / 16-bit (word) wide data bus and use only byte / word boundary addresses. all r ead accesses provide 8/16 bits of data on each bus transfer cycle. all writes take 8/16 bits of data from each bus transfer cycle. figure 1.1 block diagram : note: ** amax gl01gt = a25, amax gl512t = a24. the gl-t family combines the best features of execute in place (xip) and data storage flash memories. this family has the fast random access of xip flash along with the high density and fast program speed of data storage flash. read access to any random location takes 100 ns to 120 ns depending on device density and i/o power supply voltage. each random (initial) access reads an entire 32-byte aligned group of data called a page. other words within the same page may be re ad by changing only the low order 4 bits of word address. each access within the same page takes 15 ns to 25 ns. this is called pa ge mode read. changing any of the higher word address bits will select a different page and begin a new initial access. all read accesses are asynchronous. input/output buffers x-decoder y-decoder chip enable output enable logic erase voltage generator pgm voltage generator timer v cc detector state control command register v cc v ss v io we# wp#/acc ce# oe# stb stb dq15 - dq0 sector switches ry/by# reset# data latch y-gating cell matrix address latch ** amax ? a0 (a-1) byte#
document number: 002-00247 rev. *g page 5 of 105 s29gl01gt, s29gl512t the device control logic is subdivided into two parallel operating sections, the host interface controller (hic) and the embedd ed algorithm controller (eac). hic monitors signal levels on the device inputs and drives outputs as needed to complete read and w rite data transfers with the host system. hic delivers data from the currently entered address space on read transfers; places write transfer address and data information into the eac command memo ry; notifies the eac of power transition, hardware reset, and write transfers. the eac looks in the comm and memory, after a write transfer, for legal command sequences and performs the related embedded algorithms. changing the non-volatile data in the memory array requires a complex sequence of operations that are called embedded algorithms (ea). the algorithms are managed entirely by the devi ce internal eac. the main algo rithms perform programming and erase of the main array data. the host sy stem writes command codes to the flash device address space. the eac receives the commands, performs all the necessa ry steps to complete the command, and provides status information during the progress of an ea. the erased state of each memory bit is a logic 1. programming changes a logic 1 (high) to a logic 0 (low). only an erase operat ion is able to change a 0 to a 1. an erase operation must be performed on an entire 128-kbyte aligned and length group of data call a sector. when shipped from cy press all sectors are erased. programming is done via a 512-byte write buff er. in x16 it is possible to write from 1 to 256 words, anywhere within the write buffer before starting a programming operation. within the flash memory array, each 512-byte aligned group of 512 bytes is called a li ne. in x8 it is possible to write from 1 to 256 bytes, anywhere within the write buffer before st arting a program operation. a prog ramming operation transfers volatile data from the write buffer to a non -volatile memory array line. the operation is called write buff er programming. as the device transfers each 32-byte aligned page of data that was loaded into the write buffer to the 512-byte flash array lin e, internal logic programs an ecc code for the page into a portion of the memory array not visible to the host system software. th e internal logic checks the ecc information during the initial access of every arra y read operation. if needed, the ecc informati on corrects a one bit error during the initial access time. the write buffer is filled with 1?s after reset or the completion of any operation using the write buffer. any locations not wr itten to a 0 by a write to buffer command are by default still filled with 1?s. any 1?s in the write buffer do not affect data in the memory array during a programming operation. as each page of data that was loaded into the wr ite buffer is transferred to a memory array line. sectors may be individually protected from program and erase operations by the adv anced sector protection (asp) feature set. asp provides several, hardware and software c ontrolled, volatile and non-volatile, met hods to select which sectors are protecte d from program and erase operations. table 1.1 s29gl-t address map x16 x8 type count addresses count addresses address within page 16 a3?a0 32 a3?a-1 address within write buffer 256 a7?a0 512 a7?a-1 page 4096 per sector a15?a4 4096 per sector a15?a4 write-buffer-line 256 per sector a15?a8 256 per sector a15?a8 sector 1024 (1 gb) 512 (512 mb) amax?a16 1024 (1 gb) 512 (512 mb) amax?a16
document number: 002-00247 rev. *g page 6 of 105 s29gl01gt, s29gl512t software interface 2. address space overlays there are several separate address spaces that may appear with in the address range of the flash memory device. one address space is visible (entered) at any given time. ? flash memory array: the main non-volatile memory array used for storage of data that may be randomly accessed by asynchronous read operations. ? id/cfi: a memory array used for cypress fa ctory programmed device characteristics in formation. this area contains the device identification (id) and common flash interface (cfi) information tables. ? secure silicon region (ssr): a one time programmable (otp) no n-volatile memory array used for cypress factory programmed permanent data, and customer pr ogrammable permanent data. ? lock register: an otp non-volatile word used to configure the asp f eatures and lock the ssr. ? persistent protection bits (ppb): a non-volatile flash memory array with one bit for each sect or. when programmed, each bit protects the related sector fr om erasure and programming. ? ppb lock: a volatile register bit us ed to enable or disable programmi ng and erasure of the ppb bits. ? array password: an otp non-volatile array used to store a 64-b it password used to enable changing the state of the ppb lock bit when using password mode sector protection. ? ssr3 password: an otp non-volatile array used to st ore a 64-bit password used to enable reading the ssr3. ? dynamic protection bits (dyb): a volatile array with one bit for each sector. when set, each bit protects the related sector fr om erasure and programming. ? status register: a volatile register used to display embedded algorithm status. ? data polling status: a volatile register us ed as an alternate, legacy software co mpatible, way to display embedded algorithm status. ? ecc status: provides the status of any error detection or correction action taken when reading the selected page. the main flash memory array is the primary and default address sp ace but, it may be overlaid by one other address space, at any one time. each alternate address space is called an address space overlay (aso). each aso replaces (overlays) the entire flash device address range. any address range not defined by a particular aso address map, is reserved for future use. all read accesses outside of an aso address map returns non-valid (undefined) data. the locati ons will display actively driven data but the meaning of whatever 1?s or 0?s appear are not defined. there are four device operating modes that determine what ap pears in the flash device address space at any given time: ? read mode ? data polling mode ? status register (sr) mode ? address space overlay (aso) mode in read mode the entire flash memory array may be directly read by the host system memory controller. the memory device embedded algorithm controller (eac), puts the device in read mode during power-on, after a hardware reset, after a command reset, or after an embedded algorithm (ea) is suspended. read accesses and command wr ites are accepted in read mode. a subset of commands are accepted in read mode when an ea is suspended. while in any mode, the status register read command may be is sued to cause the status regist er aso to appear at every word address in the device address space. in this status register aso mode, the device interface waits for a read access and, any wr ite access is ignored. the next read access to the device accesses the content of the status register, ex its the status register as o, and returns to the previous (calling) mode in whic h the status register read command was received. in ea mode the eac is performing an embedded algorithm, such as programming or erasing a non-volatile memory array. while in ea mode, none of the main flash memory array is readable because the entire flash device address space is replaced by the data polling status aso. data polling status will appear at every word location in the device address space.
document number: 002-00247 rev. *g page 7 of 105 s29gl01gt, s29gl512t while in ea mode, only a program / erase suspend command or the status register read command will be accepted. all other commands are ignored. thus, no other aso may be entered from the ea mode. when an embedded algorithm is suspended, the data polling aso is visible until the device has suspended the ea. when the ea is suspended the data polling aso is exited and flash array data is available. the data polling aso is reentered when the suspended ea is resumed, until the ea is again suspended or finished. when an embedded algorit hm is completed, the data polling aso is exited and the device goes to the previous (c alling) mode (from which the em bedded algorithm was started). in aso mode, one of the remaining overlay address spaces is entered (overlaid on the main flash array address map). only one aso may be entered at any one time. commands to the device a ffect the currently entered aso. only certain commands are valid for each aso. these are listed in the table 7.1 on page 48 , in each aso related section of the table. the following asos have non-volatile data that may be programmed to change 1?s to 0?s: ? secure silicon region ? lock register ? persistent protection bits (ppb) ? password ? only the ppb aso has non-volatile data that may be erased to change 0?s to 1?s when a program or erase command is issued while one of the n on-volatile asos is entered, the ea operates on the aso. the aso is not readable while the ea is active. when the ea is completed the aso remains entered and is again readable. suspend and resume commands are ignored during an ea operating on any of these asos. 2.1 flash memory array the s29gl-t family has uniform sector archit ecture with a sector size of 128 kb. the following tables show the sector architect ure of the different devices. note: these tables have been condensed to show sector related in formation for an entire device on a single page sectors and their address ranges that are not explicitly listed (such as sa1-sa510 on the gl512t) have sectors starting and ending addresses that form the same pattern as all other sector s of that size. for example, all 128 kb sectors have the pattern xxx0000h-xxxffffh in x16 and xxx0000h-xxx1ffff in x8. table 2.1 s29gl01gt sector and memory address map sector size (kbyte) sector count sector range address range (16-bit) address range (8-bit) notes 128 1024 sa0 0000000h-000ffffh 0000000h-001ffffh sector starting address :: : ? sa1023 3ff0000h-3ffffffh 7ff0000h-7f fffffh sector ending address table 2.2 s29gl512t sector and memory address map sector size (kbyte) sector count sector range address range (16-bit) address range (8-bit) notes 128 512 sa0 0000000h-000ffffh 0000000h-001ffffh sector starting address :: : ? sa511 1ff0000h-1ffffffh 3ff0000h-3ffffffh sector ending address
document number: 002-00247 rev. *g page 8 of 105 s29gl01gt, s29gl512t 2.2 device id and cfi (id-cfi) aso there are two traditional methods for systems to identify the ty pe of flash memory installed in the system. one has traditional ly been called autoselect and is now referred to as device identificat ion (id). the other method is called common flash interface (cfi) . for id, a command is used to enable an address space overlay where up to 16 word locations can be read to get jedec manufacturer identification (id), device id , and some configuration and protection st atus information from the flash memory. th e system can use the manufacturer and device ids to select the appropriate driver software to use with the flash device. cfi also uses a command to enable an address space overlay where an extendable table of stand ard information about how the flash memory is organized and operates can be read. with this me thod the driver software does not have to be written with the specifics of each possible memory device in mind. instead the driv er software is written in a more general way to handle many different devices but adjusts th e driver behavior based on the information in the cfi table. traditionally these two address spaces have used separate commands and were separate overlays. however, the mapping of these two address spaces are non-overlapping and so can be combined in to a single address space and appear together in a single overlay. either of the traditional commands used to access (ent er) the autoselect (id) or cfi overlay will cause the now combin ed id-cfi address map to appear. the id-cfi address map appears overlays the entire flash array. the id-cfi address map starts at location 0 of the selected sector. locations above the maximum defined address of the id-cfi aso to the maximum address of the select ed sector have undefined data. the id-cfi enter commands use the same address and data values used on previous generation memories to a ccess the jedec manufacturer id (autoselect) and common flash interface (cfi) informa tion, respectively. for the complete address map see table 7.3 on page 55 . 2.2.1 device id the joint electron device engineering council (jedec) standard jep106t defines the manufacturer id for a compliant memory. common industry usage defined a method and format for readi ng the manufacturer id and a device specific id from a memory device. the manufacturer and device id information is primarily intended for programming equipment to automatically match a device with the corresponding programming algorithm. cypress has added additional fields within this 32-byte address space. the original industry format was structured to work with any memo ry data bus width e. g. x8, x16, x32. the id code values are traditionally byte wide but are located at bus width address bou ndaries such that incrementing the device address inputs will r ead successive byte, word, or double word locations with the id codes always located in the least significant byte location of the data bus. because the device data bus is word wide each code byte is located in the lower half of each word location. the original industry format made the high order byte always 0. cypress has modi fied the format to use both bytes in some words of the addre ss space. for the detail description of the device id address map see table 7.3 on page 55 . 2.2.2 common flash memory interface the jedec common flash interface (cfi) spec ification (jesd68.01) defines a standardized data structure that may be read from a flash memory device, which allows vendor-specified software algori thms to be used for entire fami lies of devices. the data stru cture contains information for sys tem configuration such as various electrical and timing parameters, and s pecial functions supported by the device. software support can then be device-independent, de vice id-independent, and forward-and-backward-compatible for entire flash device families. the system can read cfi information at the addresses within the selected sector as shown in device id and common flash interface (id-cfi) aso map on page 55 . table 2.3 id-cfi address map overview word address byte address description read / write (sa) + 0000h to 000fh (sa) + 0000h to 001fh device id (traditional autoselect values) read only (sa) + 0010h to 0079h (sa) + 0020h to 00f2h cfi data structure read only (sa) + 0080h to ffffh (sa) + 00f3h to 1ffffh undefined read only
document number: 002-00247 rev. *g page 9 of 105 s29gl01gt, s29gl512t like the device id information, cfi information is structured to work with any me mory data bus width e. g. x8, x16, x32. the co de values are always byte wide but are located at data bus width ad dress boundaries such that incrementing the device address read s successive byte, word, or double word locations with the codes al ways located in the least signif icant byte location of the dat a bus. because the data bus is word wide each code byte is located in th e lower half of each word location and the high order byte is always 0. for further information, please refer to the cfi specification, version 1.4 (or later), and the jedec publications jep137-a and jesd68.01 . please contact jedec ( www.jedec.org ) for their standards and the cfi specif ication may be found at the cypress web site ( www.cypress.com/spansionappnotes at the time of this document 's publication) or by contacting a local cypress sales office listed on the web site. 2.3 status register aso the status register aso contains a single word of registered volatile status for embedded algorithms. when the status register read command is issued, the current status is captured (by the rising edge of we#) in to the register and the aso is entered. th e status register content app ears on all word locations. the first read access ex its the status register aso (with the rising edg e of ce# or oe#) and returns to the address space map in use wh en the status register read command was issued. write commands will not exit the status register aso state. 2.4 data polling status aso the data polling status aso contains a sing le word of volatile memory indicating the progress of an ea. the data polling status aso is entered immediately follow ing the last write cycle of any co mmand sequence that initiates an ea. comm ands that initiate an ea are: ? word program ? program buffer to flash ? chip erase ? sector erase ? erase resume / program resume ? program resume enhanced method ? blank check ? lock register program ? password program ? ppb program ? all ppb erase ? evaluate erase status the data polling status word appears at all word locations in the device address space. when an ea is completed the data pollin g status aso is exited and the device address space retu rns to the address map mode where the ea was started. 2.5 secure silicon region aso the secure silicon region (ssr) provides an extra memory ar ea that can be programmed once an d permanently protected from further changes, i. e., it is a one time program (otp) area. the ssr is 2048 bytes in length. it consists of 512 bytes for factory lock ed secure silicon region (ssr0), 1024 bytes for customer locked secure silicon regions (ssr1 and ssr2), and 512 bytes for cust omer locked secure silicon region with read password (ssr3). ssr0 is shipped locked, preventing further programming. ssr1 and ssr2 are otp with each having separate lock bits and once locked no further programming is allowed for that region. ssr3 is an otp and requires a ssr3 password to read or program that region. once ssr3 is locked no further programming is allowed for that region.
document number: 002-00247 rev. *g page 10 of 105 s29gl01gt, s29gl512t the sector address supplied during the secure silicon entry comma nd selects the flash memory array sector that is overlaid by t he secure silicon region address map. the ssr is overlaid starting at location 0 in the selected se ctor. use of the sector 0 addre ss is recommended for future compatibility. while the ssr aso is entered the c ontent of all other sectors is memory core data for rea d operations. program is not allowed outside of aso. 2.6 sector protection control 2.6.1 lock register aso the lock register aso contains a single word of otp memory. when the aso is entered the lock register appears at all word locations in the device address space. however, it is recommended to read or program the lock register only at location 0 of th e device address space for future compatibility. 2.6.2 persistent protec tion bits (ppb) aso the ppb aso contains one bit of a flash memory array for each sector in the device. when the ppb aso is entered, the ppb bit for a sector appears in the least significant bit (lsb) of each address in the sector. reading any address in a sector displays data where the lsb indicates the non-volatile pr otection status for that sector. however, it is recommended to read or program the p pb only at address 0 of the sector for future compatibility. if the bit is 0 the sector is protected against programming and erase operations. if the bit is 1 the sector is not protected by the ppb. the sector may be protected by othe r features of asp. 2.6.3 ppb lock aso the ppb lock aso contains a single bit of volatile memory. the bit controls whether the bits in the ppb aso may be programmed or erased. if the bit is 0 the ppb aso is protected against progr amming and erase operations. if the bit is 1 the ppb aso is no t protected. when the ppb lock aso is entered the ppb lock bit appear s in the least significant bit (lsb) of each address in the device address space. however, it is recommended to read or pr ogram the ppb lock only at addre ss 0 of the device for future compatibility. 2.6.4 password aso the password aso contains four words of otp memory. when the aso is entered the password a ppears starting at address 0 in the device address space. all locations above the fourth word are undefined. 2.6.5 dynamic protect ion bits (dyb) aso the dyb aso contains one bit of a volatile memory array for each sector in the device. when the dyb aso is entered, the dyb bit for a sector appears in the least signific ant bit (lsb) of each address in the sector . reading any address in a sector displays data where the lsb indicates the non-volatile protection status for that sector. however, it is recommended to read, set, or clear t he dyb only at address 0 of the sector for future compatibility. if the bit is 0 the sector is protected against programming and erase operations. if the bit is 1 the sector is not protected by the dyb. the sector ma y be protected by other features of asp. table 2.4 secure silicon region word address range byte address range content region size (sa) + 0000h to 00ffh (sa) + 0000h to 01ffh factory locked secure silicon region ssr0 512 bytes (sa) + 0100h to 01ffh (sa) + 0200h to 03ffh customer locked secure silicon region ssr1 512 bytes (sa) + 0200h to 02ffh (sa) + 0400h to 05ffh customer locked secure silicon region ssr2 512 bytes (sa) + 0300h to 03ffh (sa) + 0600h to 07ffh customer locked secure silicon region with read password ssr3 512 bytes (sa) + 0400h to ffffh (sa) + 0800h to 1ffffh undefined n/a 126 kbytes
document number: 002-00247 rev. *g page 11 of 105 s29gl01gt, s29gl512t 2.7 ecc status aso the system can access the ecc status aso by issuing the ec c status entry command sequenc e during read mode. the ecc status aso provides the enabled or disabled status of the ecc function or if the ecc function correct ed a single-bit error when reading the selected page. section 5.3, automatic ecc on page 21 describes the ecc function in more detail. the ecc status aso allows the following activities: ? read ecc status for the selected page. ? aso exit. 2.7.1 ecc status the contents of the ecc st atus aso indicate, for the selected ecc page, whether the ecc logic has corrected an error in the ecc page eight bit ecc code, in the ecc page of 32-bytes of data, or that ecc is disabled for that ecc unit. the address specified in the ecc status read command, provided in table 7.1 on page 48 and table 7.2 on page 51 , selects the ecc page. table 2.5 ecc status word ? upper byte bit151413121110 9 8 name rfu rfu rfu rfu rfu rfu rfu rfu valuexxxxxxxx table 2.6 ecc status word ? lower byte bit 7654 3 2 1 0 name rfu rfu rfu rfu ecc enabled on 16-word page single bit error corrected ecc bits single bit error corrected data bits rfu value x x x x 0=ecc enabled 1=ecc disabled 0=no error corrected 1=single bit error corrected 0=no error corrected 1=single bit error corrected x
document number: 002-00247 rev. *g page 12 of 105 s29gl01gt, s29gl512t 3. data protection the device offers several features to prevent malicious or accidental modification of any sector via hardware means. 3.1 device protection methods 3.1.1 power-up write inhibit reset#, ce#, we#, and, oe# are ignored during power-on reset (por). during por, the device can not be selected, will not accept commands on the rising edge of we#, and does not drive outputs. the host interface controller (hic) and embedded algorithm controller (eac) are reset to t heir standby states, ready for reading array da ta, during por. ce# or oe# must go to v ih before the end of por (t vcs ). at the end of por the device conditions are: ? all internal configuration information is loaded, ? the device is in read mode, ? the status register is at default value, ? all bits in the dyb aso are set to un-protect all sectors, ? the write buffer is loaded with all 1?s, ? the eac is in the standby state. 3.1.2 low v cc write inhibit when v cc is less than v lko , the hic does not accept any write cycles and the eac resets. this protects data during v cc power-up and power-down. the system must provide the proper signals to the control pins to prevent unintentional writes when v cc is greater than v lko . 3.2 command protection embedded algorithms are initiated by writing command sequences into the eac command memory. the command memory array is not readable by the host system and has no aso. each host interfac e write is a command or part of a command sequence to the device. the eac examines the address and data in each write tr ansfer to determine if the write is part of a legal command sequence. when a legal command sequence is comp lete the eac will initiate the appropriate ea. writing incorrect address or data values, or writing them in an improper sequence, will generally result in the eac returning t o its standby state. however, such an improper command sequence may place the device in an unknown state, in which case the system must write the reset command, or poss ibly provide a hardware reset by driving t he reset# signal low, to return the eac t o its standby state, ready for random read. the address provided in each write may c ontain a bit pattern used to he lp identify the write as a co mmand to the device. the up per portion of the address may also select the sector address on wh ich the command operation is to be performed. the sector address (sa) includes amax through a16 flash add ress bits (system byte address signals amax through a16). a command bit pattern is located in a10 to a0 flash address bits (system byte address signals a11 through a1). the data in each write may be: a bit pattern used to help iden tify the write as a command, a code that identifies the command operation to be performed, or supply in formation needed to perform the operation. see table 7.1 on page 48 for a listing of all commands accepted by the device. 3.3 secure silicon region (otp) see section 2.5, secure silicon region aso on page 9 for a description of the secure silicon region. see section 5.4.9.3, secure silicon region aso on page 33 for a description of the allowed commands.
document number: 002-00247 rev. *g page 13 of 105 s29gl01gt, s29gl512t 3.4 sector protection methods 3.4.1 write protect signal if wp# = v il , the lowest or highest address sector is protected from program or erase operations independent of any other asp configuration. whether it is the lowest or highest sector depends on the device ordering option (model) selected. if wp# = v ih , the lowest or highest address sector is not pr otected by the wp# signal but it may be prot ected by other aspect s of asp configurati on. wp# has an internal pull-up; when unconnected, wp# is at v ih . wp# should not change between v il and v ih during any embedded operation. 3.4.2 asp advanced sector protection (asp) is a set of independent hardwar e and software methods used to disable or enable programming or erase operations, individually, in any or all sectors. this section describes the va rious methods of protecting data stored in the memory array. an overview of these methods is shown in figure 3.1 . figure 3.1 advanced sector protection overview every main flash array sector has a non-vo latile (ppb) and a vo latile (dyb) protection bit asso ciated with it. wh en either bit is 0, the sector is protected from pr ogram and erase operations. the ppb bits are protected from program and erase when the ppb lo ck bit is 0. there are two meth ods for managing the state of the ppb lock bit, persistent prot ection and password protection. password method (dq2) persistent method (dq1) lock register (one time programmable) ppb lock bit 1,2,3 64-bit password (one time protect) 1 = ppbs unlocked 0 = ppbs locked memory array sector 0 sector 1 sector 2 sector n-2 sector n-1 sector n 4 ppb 0 ppb 1 ppb 2 ppb n-2 ppb n-1 ppb n persistent protection bit (ppb) 5,6 dyb 0 dyb 1 dyb 2 dyb n-2 dyb n-1 dyb n dynamic protection bit (dyb) 7,8,9 7. 0 = sector protected, 1 = sector unprotected. 8. protect effective only if corresponding ppb is ?1? (unprotected). 9. volatile bits: defaults to user choice upon power-up (see ordering options). 5. 0 = sector protected, 1 = sector unprotected. 6. ppbs programmed individually, but cleared collectively 1. bit is volatile, and defaults to ?1? on reset (to ?0? if in password mode). 2. programming to ?0? locks all ppbs to their current state. 3. once programmed to ?0?, requires hardware reset to unlock or application of the password. 4. n = highest address sector.
document number: 002-00247 rev. *g page 14 of 105 s29gl01gt, s29gl512t the persistent protection method sets the ppb lock to 1 during por or hardware reset so that t he ppb bits are unprotected by a device reset. there is a command to clear the ppb lock bit to 0 to protect the ppb bits. there is no command in the persistent protection method to set the ppb lock bi t therefore the ppb lock bit will remain at 0 until the next power-off or hardware rese t. the persistent protection method allows boot code the option of c hanging sector protection by progra mming or erasing the ppb, then protecting the ppb from further change for the remainder of normal system operation by clearing the ppb lock bit. this is sometimes called boot-code controlled sector protection. the password method clears the ppb lock bit to 0 during por or hardware reset to protect the ppb. a 64- bit password may be permanently programmed and hidden for the password method. a comm and can be used to provide a password for comparison with the hidden password. if the password matches the ppb lock bit is set to 1 to unprotect the ppb. a comm and can be used to clear the ppb lock bit to 0. the selection of the ppb lock manag ement method is made by progra mming otp bits in the lock regi ster so as to permanently select the method used. the lock register also contains otp bits, for protecting the ssr. the ppb bits are erased so that all main fl ash array sectors are unprotected when sh ipped from cypress. the secured silicon region can be factory protected or left unprotecte d depending on the ordering option (model) ordered. 3.4.3 ppb lock the persistent protection bit lock is a vo latile bit for protecting a ll ppb bits. when cleared to 0, it locks all ppbs and when set to 1, it allows the ppbs to be changed. there is only one ppb lock bit per device. the ppb lock command is used to cl ear the bit to 0. the ppb lock bit must be clear ed to 0 only after all the ppbs are configure d to the desired settings. in persistent protection mode, the ppb lock is set to 1 during por or a hardware reset. when cleared, no software command sequence can set the ppb lock, on ly another hardware reset or po wer-up can set t he ppb lock bit. in the password protection mode, the ppb lock is cleared to 0 during por or a hardware reset. the ppb lock can only set to 1 by the password unlock command sequence. the ppb lock can be cleared by the ppb lock bit clear command. 3.4.4 persistent prot ection bits (ppb) the persistent protection bits (ppb) are lo cated in a separate nonvolat ile flash array. one of the ppb bits is assigned to each sector. when a ppb is 0 its related sector is protected from program and erase operat ions. the ppb are programmed individually but must be erased as a group, similar to the way individual words may be programmed in the main array but an entire sector mus t be erased at the same time. preprogramming and veri fication prior to erasure are handled by the eac. programming a ppb bit requ ires the typical word programm ing time. during a ppb bit programmi ng operation or ppb bit erasing, data polling status dq6 toggle bit i will toggle until the operati on is complete. erasing all the ppbs requires typical sector erase time. if the ppb lock is 0, the ppb program or erase commands do not execute and time-out without programming or erasing the ppb. the protection state of a ppb for a given sector can be verified by executing a ppb status read command when entered in the ppb aso. 3.4.5 dynamic prot ection bits (dyb) dynamic protection bits are volatile and unique for each sect or and can be individually modified. dybs only control protection for sectors that have their ppbs erased. by i ssuing the dyb set or clear command sequences, the dyb are set to 0 or cleared to 1, thus placing each sector in th e protected or unprotected state respectively, if the ppb for that sector is 1. this feature allo ws software to easily protect sectors against inadvertent changes, ye t does not prevent the easy removal of protection when change s are needed. the dyb can be set to 0 or cleared to 1 as often as needed.
document number: 002-00247 rev. *g page 15 of 105 s29gl01gt, s29gl512t 3.4.6 sector protect ion states summary each sector can be in one of the following protection states: ? unlocked ? the sector is unprotected and pr otection can be changed by a simple command. the protection state defaults to unprotected after a power cycle or hardware reset. ? dynamically locked ? a sector is protected and protection can be changed by a simple command. the protec tion state is not saved across a power cycle or hardware reset. ? persistently locked ? a sector is protected and protection can only be changed if the ppb lock bit is set to 1. the protection state is non-volatile and saved across a power cycle or hardware reset. changing the protection state requires programming or erase of the ppb bits. 3.4.7 lock register the lock register holds the non-volatile otp bits for cont rolling protection of the ssr and determining the ppb lock bit management method (protection mode). the secure silicon region (ssr) protection bits must be used wit h caution, as once locked, there is no procedure available for unlocking the protected portion of the secure silicon region and n one of the bits in the protected secure silicon region memory space can be modified in any way. once the secure silicon region area is protected, an y further attempts to program in the area will fail with status indicating the area being programmed is protected. the region 0 indi cator bit is located in the lock register at bit location 0, region 1 in bit location 6, region 2 in bit location 9, and region 3 in bit location 10. table 3.1 sector protection states protection bit values sector state ppb lock ppb dyb 1 1 1 unprotected ? ppb and dyb are changeable 1 1 0 protected ? ppb and dyb are changeable 1 0 1 protected ? ppb and dyb are changeable 1 0 0 protected ? ppb and dyb are changeable 0 1 1 unprotected ? ppb not changeable, dyb is changeable 0 1 0 protected ? ppb not changeable, dyb is changeable 0 0 1 protected ? ppb not changeable, dyb is changeable 0 0 0 protected ? ppb not changeable, dyb is changeable table 3.2 lock register bit default value name 15-12 1 reserved 11 1 ssr region 3 password protection mode lock bit 10 1 ssr region 3 (customer) lock bit 9 1 ssr region 2 (customer) lock bit 80reserved 7 1 reserved 6 1 ssr region 1 (customer) lock bit 51reserved 41reserved 31reserved 2 1 password protection mode lock bit 1 1 persistent protection mode lock bit 0 0 ssr region 0 (factory) lock bit
document number: 002-00247 rev. *g page 16 of 105 s29gl01gt, s29gl512t as shipped from the factory, all devices default to the persis tent protection method, with all sectors unprotected, when power is applied. the device programmer or host system can then choose wh ich sector protection method to use. programming either of the following two, one-time programmable, non-volatile bits, locks the part permanently in that mode: ? persistent protection mode lock bit (dq1) password protection mode lock bit (dq2) if both lock bits are se lected to be programmed at the same time, the operation will ab ort. once the password mode lock bit is program med, the persistent mode lock bit is pe rmanently disabled and no changes to the protection scheme are allowed. similarly, if the persistent mode lock bit is programmed, the password mode is permanently disabled. if the password mode is to be chosen, the password must be progr ammed prior to setting the corresponding lock register bit. set ting the password protection mode lock bit (dq2) will disable the ability to program or read the password. the programming time of the lock register is the same as the typical word programming time. during a lock register programming ea, data polling status dq6 toggle bit i will toggle until the programming has complete d. the system can also determine the sta tus of the lock register programming by reading the status register. see status register on page 36 for information on these status bits. the user is not required to program dq2 or dq1, and dq6 or dq0 bi ts at the same time. this allows the user to lock the ssr befo re or after choosing the device protection scheme. when progra mming the lock bits, the reserved bits must be 1 (masked). 3.4.8 persistent protection mode the persistent protection method sets the ppb lock to 1 during por or hardware reset so that t he ppb bits are unprotected by a device reset. there is a command to clear the ppb lock bit to 0 to protect the ppb. there is no command in the persistent protection method to set the ppb lock bit to 1 therefore the ppb lock bit will remain at 0 until th e next power-off or hardware reset. 3.4.9 password protection mode 3.4.9.1 ppb password protection mode ppb password protection mode a llows an even higher level of se curity than the persistent sector protection mode, by requiring a 64-bit password for setting the ppb lock. in addition to this password requirement, after power up and re set, the ppb lock is cleared to 0 to ensure protection at pow er-up. successful execution of the password unlock command by entering the entire password sets the ppb lock to 1, a llowing for sector ppb modifications. password protection notes: ? the password program command is only capable of programming 0?s. ? the password is all 1?s when shipped from cypress. it is located in its own memory space and is accessible through the use of t he password program and password read commands. ? all 64-bit password combinations are valid as a password. ? once the password is programmed and verified, the password mode locking bit must be set in order to prevent reading or modification of the password. ? the password mode lock bit, once programmed, prevents reading the 64-bit password on the data bus and further password programming. all further read commands to the password region are disabled (data is read as 1?s). there is no means to verify what the password is after the password protection mode lock bit is programmed. password verification is only allowed before selecting the password protection mode. an y program operation will fail and will repor t the results as a normal program failure on a locked sector. ? the password mode lock bit is not erasable.
document number: 002-00247 rev. *g page 17 of 105 s29gl01gt, s29gl512t ? the exact password must be entered in order for the unlocking function to occur. ? the addresses can be loaded in any order but all 4 words are required for a successful match to occur. ? the sector addresses (amax?a16) and word line addresses (a15?a8) are compared to ?zero? while the password address/ data are loaded. if the sector address or word line address don ?t match then the error will be r eported at the end of that writ e cycle. the status register will return to t he ready state with the program status bit set to 1 and write bu ffer abort status bi t set to 1 indicating a failed programming operation. the data polling status will remain active, with dq7 set to the complement of the dq7 bit in the last word of the password unlo ck command, and dq6 toggling. ry/by# will remain low. ? the specific address and data are compared after the program buffer to flash command has bee n given. if they don?t match to the internal set value than the status register will return to the ready state with the program status bit set to 1 indicati ng a failed programming operation. the data polling status will remain active, with dq7 set to the comp lement of the dq7 bit in the last word of the password unlock command, and dq6 toggling. ry/ by# will remain low. in this error case due to incorrect password, the device requires a wait time of t ppb and a software reset command to clear the error prior to the password aso exit command to properly exit the password aso. failure to do so will cause the device to remain in the password aso. ? the device requires t ppb for setting the ppb lock after the valid 64-bit passw ord is given to the devi ce.this makes it take an unreasonably long time (58 million years) for a hacker to run th rough all the 64-bit combinations in an attempt to correctly ma tch a password. the ea status checking methods may be used to determine when the eac is ready to accept a new password command. ? if the password is lost after sett ing the password mode lock bit, there is no way to clear the ppb lock.
document number: 002-00247 rev. *g page 18 of 105 s29gl01gt, s29gl512t 4. read operations 4.1 asynchronous read each read access may be made to any location in the memory (random access). each random access is self-timed with the same latency from ce# or address to valid data (t acc or t ce ). 4.2 page mode read each random read accesses an entire 32-byte page in parall el. subsequent reads within the same page have faster read access speed. the page is selected by the higher add ress bits (amax-a4), while the specific word of that page is selected by the least significant address bits a3-a0 (a3-a-1 in x8 mode). the higher addr ess bits are kept constant and only a3-a0 (a3-a-1 in x8 mode ) changed to select a different word in the same page. this is an asynchronous access with data appearing on dq15-dq0 (dq7-dq0 in x8 mode) when ce# remains low, oe# remains low, and the asynchronous page access time (t pacc ) is satisfied. if ce# goes high and returns low for a subsequent access, a random read access is performed and time is required (t acc or t ce ).
document number: 002-00247 rev. *g page 19 of 105 s29gl01gt, s29gl512t 5. embedded operations 5.1 embedded algorithm controller (eac) the eac takes commands from the host system for programming and erasing the flash memory array and performs all the complex operations needed to change the non-volati le memory state. this frees the host syst em from any need to manage the program and erase processes. there are four eac operation categories: ? standby (read mode) ? address space switching ? embedded algorithms (ea) ? advanced sector protection (asp) management 5.1.1 eac standby in the standby mode current consumption is greatly reduced. the eac enters its standby mode when no command is being processed and no embedded algorithm is in progress. if the device is deselected (ce# = high) during an embedded algorithm, the device still draws active current until t he operation is completed (i cc3 ). i cc4 in dc characteristics on page 68 represents the standby current s pecification when both t he host interface and eac are in their standby state. 5.1.2 address space switching writing specific address and data sequences (command sequences) switch the memory device address space from the main flash array to one of the address space overlays (aso). embedded algorithms operate on the information visible in the cu rrently active (entered) aso. th e system continues to have acce ss to the aso until t he system issues an aso exit command, performs a hardware reset , or until power is removed from the device. an aso exit command switches from an aso back to the ma in flash array address space. the commands accepted when a particular aso is entered are listed between the aso ente r and exit commands in the command definitions table. see command summary on page 48 for address and data requirements for all command sequences. 5.1.3 embedded algorithms (ea) changing the non-volatile data in the memory array requires a complex sequence of operations that are called embedded algorithms (ea). the algorithms are managed entirely by the device internal embedded algorithm controller (eac). the main algorithms perform programming an d erasing of the main array da ta and the aso?s. the host system writes command codes to the flash device address space. the eac receives the commands, per forms all the necessary steps to complete the command, and provides status information during the progress of an ea. 5.2 program and erase summary flash data bits are erased in parallel in a large group called a sector. the erase operation places each data bit in the sector in the logical 1 state (high). flash data bits ma y be individually programmed from the erased 1 state to the programmed logical 0 (low ) state. a data bit of 0 cannot be programmed back to a 1. a succeeding read shows that the data is still 0. only erase operation s can convert a 0 to a 1. programming the same word location more than once with different 0 bits will result in the logical and of t he previous data and the new data being programmed. the dur ation of program and erase operations is shown in embedded algorithm performance table on page 44 .
document number: 002-00247 rev. *g page 20 of 105 s29gl01gt, s29gl512t program and erase operations may be suspended. ? an erase operation may be suspended to allow either programming or reading of another sector (not in the erase sector). no other erase operation can be started during an erase suspend. ? a program operation may be suspended to allow reading of another location (not in the line being programmed). ? no other program or erase operation may be started during a suspended program operation ? program or erase commands will be ignored during a suspended program operation. ? after an intervening program operation or read access is comp lete the suspended erase or program operation may be resumed. the resume can happen at any time after the suspend, assuming the device is not in the proce ss of executing another command. ? program and erase operations may be interr upted as often as necessary but in orde r for a program or erase operation to progress to completion there must be some periods of time between resume and the next sus pend commands greater than or equal to t prs or t ers in embedded algorithm performance table on page 44 . ? when an embedded algorithm (ea) is complete, the eac return s to the operation state and address space from which the ea was started (erase suspend, eac standby, ...). the system can determine the status of a program or erase opera tion by reading the status regist er or using data polling status . refer to status register on page 36 for information on these status bits. refer to data polling status on page 37 for more information. any commands written to the device during the embedded program algorithm are ignored except the program suspend (x51h), status read command (x70h), and erase suspend/program suspend command (xb0h). any commands written to the device during the embedded erase al gorithm are ignored except st atus read (x70h) and erase suspend/program suspend command (xb0h). a hardware reset immediately terminates any in progress program / erase operation and returns to read mode after t rph time. the terminated operation should be reinitiated once the device has returned to the idle state, to ensure data integrity. for performance and reliability reasons reading and prog ramming is internally done on full 32-byte pages. i cc3 in dc characteristics on page 68 represents the active curr ent specification for a write (embedded algorithm) operation. 5.2.1 program granularity the s29gl-t supports two methods of programming, word or writ e buffer programming. each page can be programmed by either method. pages programmed by different methods may be mixed wit hin a line for the industrial temperature version (-40c to +85c). for the industrial plus version (-40c to +105c) and extended version (-40c to +125c) the device will only support o ne programming operation on each 32-byte page between erase operat ions and single word programming command is not supported. word programming examines the data word supplied by the co mmand and programs 0?s in the addressed memory array word to match the 0?s in the command data word. write buffer programming examines the write buffer and programs 0? s in the addressed memory array pages to match the 0?s in the write buffer. the write buffer doe s not need to be completely fill ed with data. it is allowed to program as little as a single bit, several bits, a single word, a few words, a page, multiple pages, or the en tire buffer as one programming operation. use of the write b uffer method reduces host system overhead in writing program commands and reduces memory device internal overhead in programming operations to make write buffer programming more ef ficient and thus faster than programming individual words with the word programming command. 5.2.2 incremental programming the same word location may be programmed more than once, by either the word or write buffer programming methods, to incrementally change 1?s to 0?s. note that more than one pr ogramming operation on the same page will disable ecc for that page.
document number: 002-00247 rev. *g page 21 of 105 s29gl01gt, s29gl512t 5.3 automatic ecc 5.3.1 ecc overview the automatic ecc feature works transparently with normal prog ram, erase, and read operations. as the device transfers each page of data from the write buffer to the memory array, internal ecc logic programs e cc code for the page into a portion of the memory array that is not visible to the host system. the device evaluates the page data and the e cc code during each initial pa ge access. if needed, the internal ecc logic will correct a one bit error during the initial access. programming more than once to a particular page will disable the ecc function for that page. the ecc function will remain disab led for that page until the next time the host system erases the sector co ntaining that page. the host system may read data stored in that page following multiple programming operations; however, ecc is disabled and an error in that page will not be detected or corrected. 5.3.2 program and erase summary for performance and reliability reasons, reading and programming operations are performed on full 32-byte pages in parallel. th e device provides ecc on each page by adding an ecc code to ea ch page when first programmed. the ecc code is automatic and transparent to the host system. 5.3.3 ecc implementation each 32-byte page in the main flash array, as well as each 32 -byte otp region, features an associated ecc code. internal ecc logic is able to detect and correct any single bit error found in a page, or the associated ecc code, during a read access. the first write buffer program operation applied to a page pr ograms the ecc code for that page. subsequent programming operations, that occur more than once, on a particular page di sable the ecc function for that page. this allows bit or word programming; however, note that multiple programming operations to the same page will disable the ecc function on the page where incremental programming occurs. an erase of the sector containing a page with ecc disabled will re-enable the ecc function for that page. the ecc function is automatic an d transparent to the user. the transparency of the automatic ecc function enhances data integri ty for typical programming operations that write data once to each page. the ecc function also facilitates software compatibility to previous generations of gl family products by allowing single wo rd programming and bit walking where the same page or word is programmed more than once. when a page has automatic ecc disabled , the ecc function will not detect or correct an error on a data read from that page. 5.3.4 word programming word programming programs a single word anywhere in the main flash memory array. programming multiple words in the same 32-byte page disables automatic ecc protecti on on that page. a sector eras e of the sector containing that page will re-enable automatic ecc following multiple word programming operations on that page. 5.3.5 write buffer programming each write buffer program operation allows for programming of 1 bit up to 512 bytes. a 32-byte page is the smallest program granularity that features automatic ecc protection. programming the same page more than once will disable the automatic ecc function on that page. cypress recommends that a write buffer progra mming operation program multiple pages in an operation and write each page only once. this keeps the automatic ecc protection enabled on each page. for the very best performance, program in full lines of 512 bytes aligned on 512-byte boundaries.
document number: 002-00247 rev. *g page 22 of 105 s29gl01gt, s29gl512t 5.4 command set 5.4.1 program methods 5.4.1.1 word programming word programming is used to program a single wo rd anywhere in the main flash memory array. the word programming command is a four-write-cycle sequence. the program command sequence is initiated by writing two unlock write cycles, followed by the program set up command. the pr ogram address and data are written next, which in turn initi ate the embedded word program algorithm. the sy stem is not required to provide further co ntrols or timing. the device automatically generates the program pulses and verifies the programmed cell margin internally. when the embedded word program algorithm is complete, the eac then returns to its standby mode. the system can determine the status of th e program operation by using data polling status, reading the status register, or monitoring the ry/by# output. see status register on page 36 for information on th ese status bits. see data polling status on page 37 for information on these status bits. see figure 5.1 on page 22 for a diagram of the word programming operation. any commands other than program suspend writ ten to the device during the embedded progr am algorithm are ignored. note that a hardware reset (reset# = v il ) immediately terminates the programming operation and returns the device to read mode after t rph time. to ensure data integrity, the program command sequence s hould be reinitiated once the device has completed the hardware reset operation. a modified version of the word programming command, without unlock write cycles, is used for pr ogramming when ent ered into the lock register, password, and ppb asos or the unlock bypass mode . the same command is used to change volatile bits when entered in to the ppb lock, and dyb asos. see table 7.1 on page 48 for program command sequences. figure 5.1 word program operation start write program command sequence data poll from system verify word? last addresss? increment address embedded program algorithm in progress programming completed no no yes yes
document number: 002-00247 rev. *g page 23 of 105 s29gl01gt, s29gl512t 5.4.1.2 write buffer programming a write buffer is used to program data within a 512-byte address range aligned on a 512-byte boundary (line). thus, a full writ e buffer programming operation must be aligned on a line boundary. programming operations of less than a full 512 bytes may start on any word boundary but may not cross a line boundary. at the start of a write buffer programming operation all bit locations in the buffer are all 1?s (ffffh words) thus any locations not loaded will retain the existing data. see product overview on page 4 for information on address map. write buffer programming allows up to 512 bytes to be programmed in one operation. it is possible to program from 1 bit up to 5 12 bytes in each write buffer programming operat ion. it is recommended that a multiple of pages be written and each page written o nly once. for the very best performance, programming should be do ne in full lines of 512 bytes aligned on 512-byte boundaries. write buffer programming is supported only in the main flash array or the ssr aso. the write buffer programming operation is in itiated by first writing two unlock cycles. this is followed by a third write cycle of the write to buffer command with the sector address (sa), in which pr ogramming is to occur. next, th e system writes the number of word locations minus 1. this tells the device how many writ e buffer addresses are loaded with data and therefore when to expect the program buffer to flash confirm command. the sector address must match in the write to buffer command and the write word count command. the sector to be pr ogrammed must be unlocked (unprotected). the system then writes the starting addre ss / data combination. this starting add ress is the first address / data pair to be programmed, and selects the write-buffer-line addr ess. the sector address must match the write to buffer sector address or the operation will abort and goes to the abort state. all subsequent address / data pairs must be in sequential order. all write bu ffer addresses must be within the same line. if the system attempts to load data outside this range, the operation will abort and go to the abort state. the counter decrements for each data load operation. note that while counting down the data writes, every write is considered t o be data being loaded into the write buffer. no commands are possible during the write buffer loading period. the only way to stop loading the write buffer is to write with an address that is outside the line of t he programming operation. this invalid addres s will immediately abort the wr ite to buffer command. once the specified number of write buffer locations has been loaded, the system must then write the program buffer to flash command at the sector address. the device then goes busy . the embedded program algorithm automatically programs and verifies the data for the corre ct data pattern. the system is not required to pr ovide any controls or timings during these oper ations. if an incorrect number of write buffer locations have been loaded the operation will abort and goes to the abort state. the abort occurs when anything other than the program buffer to flash is written when that command is expected at the end of the word count. the write-buffer embedded programming operation can be susp ended using the program suspend command. when the embedded program algorithm is complete, the eac then returns to the eac standby or erase suspend st andby state where the programming operation was started. the system can determine the status of th e program operation by using data polling status, reading the status register, or monitoring the ry/by# output. see status register on page 36 for information on th ese status bits. see data polling status on page 37 for information on these status bits. see figure 5.2 on page 24 for a diagram of the programming operation. the write buffer programming sequence will be aborted under the following conditions: ? load a word count value greater than the buffer size (255). ? write an address that is outside the line provided in the write to buffer command. ? the program buffer to flash command is not issued after the write word count number of data words is loaded. when any of the conditions that cause an abort of write buffer command occur the abort will happen immediately after the offend ing condition, and will indicate a program fail in the status regist er at bit location 4 (psb = 1) due to write buffer abort bit lo cation 3 (wbasb = 1). the next successful program oper ation will clear the failure status or a cle ar status register may be issued to cl ear the psb status bit. the write buffer programming sequence can be stopped by the follo wing: hardware reset or power cycle. however, these using either of these methods may leave the area being programmed in an intermediate state with invalid or unstable data values. in t his case the same area will need to be reprogrammed with the same data or erased to ensure data values are properly programmed or erased.
document number: 002-00247 rev. *g page 24 of 105 s29gl01gt, s29gl512t figure 5.2 write buffer programming operat ion with data polling status notes: 1. dq7 should be rechecked even if dq5 = 1 because dq7 may change simultaneously with dq5. 2. if this flowchart location was reached because dq5 = 1, then the device failed. if this flowchart location was reached becaus e dq1 = 1, then the write buffer operation was aborted. in either case the proper reset command must be written to the device to return the device to read mode. write-buffer-programming- abort-rest if dq1 = 1, either software reset or write-buffer-programming-abort-reset if dq5 = 1. 3. see table 7.1, command definitions x16 on page 48 for the command sequence as required for write buffer programming. 4. when sector address is specified, any address in the selected sector is acceptable. however, when loading write-buffer addres s locations with data, all addresses must fall within the selected write-buffer page. write ?write to buffer? command sector address write ?word count? to program - 1 (wc) sector address write starting address/data wc = 0? abort write to buffer operation? write to a different sector address write to buffer aborted. must write ?write-to-buffer abort reset? command sequence to return to read mode. write next address/data pair wc = wc - 1 write program buffer to flash confirm, sector address read dq7-dq0 with addr = last loaded address dq7 = data? dq5 = 1? dq1 = 1? read dq7-dq0 with addr = last loaded address dq7 = data? fail or abort ( note 2 ) pass no yes (note 4) no no no no no yes yes yes yes yes
document number: 002-00247 rev. *g page 25 of 105 s29gl01gt, s29gl512t figure 5.3 write buffer programming oper ation with status register notes: 1. see table 7.1, command definitions x16 on page 48 for the command sequence as required for write buffer programming. 2. when sector address is specified, any address in the selected sector is acceptable. however, when loading write-buffer addres s locations with data, all addresses must fall within the selected write-buffer page. write ?write to buffer? command sector address write ?word count? to program - 1 (wc) sector address write starting address/data wc = 0? abort write to buffer operation? write to a different sector address write to buffer aborted. must write ?write-to-buffer abort reset? command sequence to return to read mode. write next address/data pair wc = wc - 1 write program buffer to flash confirm, sector address read status register drb sr[7] = 0? wbasb sr[3] = 1? psb sr[4] = 0? program fail program successful no yes (note 2) no no no yes yes yes no yes program aborted during write to buffer command slsb sr[1] = 0? no yes sector locked error program fail
document number: 002-00247 rev. *g page 26 of 105 s29gl01gt, s29gl512t legend: sa = sector address (non-sector address bits are don't care. any address within the sector is sufficient.) wbl = write buffer location (must be within the boundaries of the write-buffer-line specified by the starting address.) wc =word count pd = program data 5.4.2 program suspend / pr ogram resume commands the program suspend command allows the system to interrupt an embedded programming operation so that data can read from any non-suspended line. when the program suspend command is wr itten during a programming process, the device halts the programming operation within t psl (program suspend latency) and updates the status bits. addresse s are don't-cares when writing the program suspend command. there are two commands available for program suspend. the le gacy combined erase / program suspend command (b0h command code) and the separate program suspend command (51h command c ode). there are also two commands for program resume. the legacy combined erase / program resume command (30h comm and code) and the separate program resume command (50h command code). it is recommended to use the separate progra m suspend and resume commands for programming and use the legacy combined command only for erase suspend and resume. after the programming operation has been su spended, the system can read array data from any non-suspended line. the program suspend command may also be issued during a programming operation while an erase is suspended. in this case, data may be read from any addresses not in erase suspend or program suspend. after the program resume command is writt en, the device reverts to programming and t he status bits are upda ted. the system can determine the status of the program operation by reading the status register or using data polling. refer to status register on page 36 for information on these status bits. refer to data polling status on page 37 for more information. accesses and commands that are valid during program suspend are: ? read to any other non-erase-suspended sector ? read to any other non-program-suspended line ? status read command ? status register clear ? exit aso or command set exit ? program resume command table 5.1 write buffer programming command sequence sequence x16 x8 comment address data address data issue unlock command 1 555 aa aaa aa issue unlock command 2 2aa 55 555 55 issue write to buffer command at sector address sa 0025h sa 25h issue number of locations at sector address example: wc of 0 = 1 word to pgm wc of 1 = 2 words to pgm sa wc sa wc wc = number of words to program ? 1 (in x8 mode wc = number of bytes to program ? 1) load starting address / data pair starting address pd starting address pd selects write-buffer-page and loads first address/data pair. load next address / data pair wbl pd wbl pd all addresses must be within the selected write-buffer-page boundaries, and have to be loaded in sequential order. load last address/data pair wbl pd wbl pd all addresses must be within the selected write-buffer-page boundaries, and have to be loaded in sequential order. issue write buffer program confirm at sector address sa 0029h sa 29h this command must follow the last write buffer location loaded, or the operation will abort. device goes busy.
document number: 002-00247 rev. *g page 27 of 105 s29gl01gt, s29gl512t the system must write the program resu me command to exit the program suspend mode and continue the programming operation. further writes of the program resume command ar e ignored. another program suspend command can be written after the device has resumed programming. program operations can be interrupted as o ften as necessary but in order for a program operation to progress to completion ther e must be some periods of time between resume and the next suspend command greater than or equal to t prs in embedded algorithm controller (eac) on page 19 . program suspend and resume is not supported while entered in an aso. 5.4.3 accelerated programming the device supports program oper ations when the system asserts v hh on the wp#/acc or acc pin. when wp#/acc or acc pin is lowered back to v ih or v il the device exits the accelerated programming mode and returns to normal operation. the wp#/acc is v hh tolerant but is not designed to accelerate the program functions. if the system asserts v hh on this input, the device automatically enters the unlock bypass mode. the system can then use the write buffer load co mmand sequence provided by the unlock bypass mode. note that if a ?write-to-buffer-abort reset? is required while in unlock bypass mo de, the full 3-cycle rese t command sequence must be used to reset the device. removing v hh from the acc input, upon completion of the embedded program operation, returns the device to normal operation. note that the wp#/acc pin must not be at v hh for operations other than accelerated programming, or device damage may result. wp# cont ains an internal pull-up; when unconnected, wp# is at v ih . accelerated programming is support ed at room temperature only. ? sectors must be unlocked prio r to raising wp#/acc to v hh . ? it is recommended that wp#/acc apply v hh after power-up sequence is completed. in addition, it is recommended that wp#/ acc apply from v hh to v ih /v il before powering down v cc /v io . 5.4.4 unlock bypass this device features an unlock bypass mode to facilitate shor ter programming commands. once the device enters the unlock bypass mode, only two write cycles are required to program data , instead of the normal four cycles.the device will also support the write to buffer command and will only require four+ write cycles. this mode dispenses with the initial two unlock cycles required in the standard program command sequence, resulting in faster t otal programming time. the command summary on page 48 shows the requirements for the unlock bypass command sequences. during the unlock bypass mode, only the read, program, write buffer prog ramming, write-to-buffer-abo rt reset, status register read, status register clear, soft reset, unlock bypass sector erase, unlock bypass chip erase, unlock erase suspend/resume, unlock bypass suspend/resume, and unlock bypass reset commands ar e valid. to exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset command sequence. the firs t cycle address is ?don't care? and the data 9 0h. the second cycle need only contain the data 00h. the se ctor then returns to the read mode. software functions and sample code the following are c source code examples of using the unlock bypass entry, prog ram, and exit functions. refer to the cypress low level driver user?s guide for general information on cypress flash memory software development guidelines. table 5.2 unlock bypass entry (lld function = lld_unlockbypassentrycmd) cycle description operation byte address word adddress data 1 unlock write base + aaah base + 555h 00aah 2 unlock write base + 555h base + 2aah 0055h 3 entry command write base + aaah base + 555h 0020h
document number: 002-00247 rev. *g page 28 of 105 s29gl01gt, s29gl512t /* example: unlock bypass entry command */ *( (uint16 *)base_addr + 0x555 ) = 0x00aa; /* write unlock cycle 1 */ *( (uint16 *)base_addr + 0x2aa ) = 0x0055; /* write unlock cycle 2 */ *( (uint16 *)base_addr + 0x555 ) = 0x0020; /* write unlock bypass command */ /* at this point, programming only takes two write cycles. */ /* once you enter unlock bypass mode, do a series of like */ /* operations (programming or sector erase) and then exit */ /* unlock bypass mode before beginning a different type of */ /* operations. */ /* example: unlock bypass program command */ /* do while in unlock bypass entry mode! */ *( (uint16 *)base_addr ) = 0x00a0; /* write program setup command */ *( (uint16 *)pa ) = data; /* write data to be programmed */ /* poll until done or error. */ /* if done and more to program, */ /* do above two cycles again. */ /* example: unlock bypass exit command */ *( (uint16 *)base_addr ) = 0x0090; *( (uint16 *)base_addr ) = 0x0000; 5.4.5 evaluate erase status the evaluate erase status (ees) command verifies that the last erase operati on on the addressed sector was completed successfully (i.e. ?trust worthy?). the ee s command can be used to detect erase operations failed due to loss of power, reset, or failure during the erase operation. to initiate a ees on a sector, write 35h to address 555h in the sector, while the eac is in the standby state. the ees command may not be written while the device is actively programming or erasing or suspended. the ees command does not allow for reads to t he array during the operation. use the status register or polli ng method (only dq6 toggles) to determine if the device is busy or completed. once completed us e the status register read to confirm if t he sector is trust worthy or not. bit 5 of the status register (s r[5]) will be cleared to 0 if the sector is trust worthy. if the sector is not trust worthy than sr[5] will be set to 1, rd/by# will stay lo w, and either a softw are reset / aso exit command or a status register clear command is required to return the device to the standby state. once the ees is completed, the eac will return to the standby state. the ees command requires t ees to complete and update the erase status in sr . the drb bit (sr[7]) may be read to determine when the ees command is finished. if a sector is found not erased with sr[5]=1, the sector must be erased again to ensure relia ble storage of data in the sector. table 5.3 unlock bypass program (lld function = lld_unlockbypassprogramcmd) cycle description operation byte address word adddress data 1 program setup write base + xxxh base + xxxh 00a0h 2 program command write program addr ess program address program data table 5.4 unlock bypass reset (lld function = lld_unlockbypassresetcmd) cycle description operation byte address word adddress data 1 reset cycle 1 write base + xxxh base + xxxh 0090h 2 reset cycle 2 write program address program address 0000h
document number: 002-00247 rev. *g page 29 of 105 s29gl01gt, s29gl512t 5.4.6 blank check the blank check command will confirm if the selected main flash a rray sector is currently erased (i.e. ?trust worthy? and ?blan k?). the blank check command does not allow for reads to the array durin g the blank check. reads to the array while this command is executing will return polling data. to initiate a blank check on a sector, write 33h to address 555h in the sector, while the eac is in the standby state. the blank check command may not be written while the device is actively programming or erasing or suspended. use the status register or po lling method (equivalent to an embedded erase operation) to determine if the device is busy or completed. once completed the status register and the polling me thod will display if the sector is blank (equivalent to a succe ssful erase operation) or if the sector is not er ased. bit 5 of the status register (sr[5]) will be cleared to 0 if the sector is bla nk. if the sector is not blank than sr[5] will be set to 1, rd/by# will stay low, and either a so ftware reset / aso exit command or a stat us register clear command is required to return the device to the standby state. as soon as any bit is found to not be erased, the device will halt t he operation and report the results. once the blank check is completed, the eac will return to the standby state. 5.4.7 erase methods 5.4.7.1 chip erase the chip erase function er ases the entire main flash memory array. the devic e does not require the system to preprogram prior t o erase. the embedded erase algorithm automatic ally programs and verifies the entire memory for an all 0 data pattern prior to electrical erase. after a successf ul chip erase, all loca tions within the device contain ffffh. the system is not required to p rovide any controls or timings during these oper ations. the chip erase command sequence is initiated by writing two unlock cycles, followed by a set up command. two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the embedded erase algorithm. when we# goes hi gh, at the end of the 6th cycle, the ry/by# goes low. when the embedded erase algorithm is complete, the eac returns to the standby state. note that while the embedded erase operation is in progress, the system can not read data from t he device. the system c an determine the status of the erase operat ion by reading the ry/by#, status regist er or using data polling. refer to ready/busy# (ry/by#) on page 61 for information on ry/ by#. refer to status register on page 36 for information on these status bits. refer to data polling status on page 37 for more information. once the chip erase operation has begun, only a status read, hardware reset or power cycle are vali d. all other commands are ignored. however, a hardware reset or power cycle immediately terminates the erase operation and returns to read mode after t rph time. if a chip erase operation is terminated, the chip er ase command sequence must be re initiated once the device has returned to the idle state to ensure data integrity. see table 5.7 on page 44 , asynchronous write operations on page 82 and alternate ce# controlled write operations on page 88 for parameters and timing diagrams. sectors protected by the asp dyb an d ppb bits will not be erased. see asp on page 13 . if a sector is protected during chip erase, chip erase will skip the protected sector and continue with next sector erase. the status regist er erase status bit and sector lock bit are not set to 1 by a failed erase on a protected sector.
document number: 002-00247 rev. *g page 30 of 105 s29gl01gt, s29gl512t 5.4.7.2 sector erase the sector erase function erases one sector in the memory array. the device does not require the system to preprogram prior to erase. the embedded erase algorithm automatic ally programs and verifies the entire se ctor for an all 0 data pattern prior to electrical erase. after a successf ul sector erase, all locations within the eras ed sector contain ffffh. the system is not requ ired to provide any controls or timings during these operations. the sect or erase command sequence is initiated by writing two unlock cycles, followed by a set up command. two additional unlock write cycles are then followed by the add ress of the sector to be erased, and the sector erase command. when we# goes high, at the end of the 6th cycle, the ry/by# goes low. after the command sequence is written, a sector erase time-out of t sea occurs. during the time-out period, additional sector addresses and sector erase commands may be written. invalid co mmands will be ignored during the time-out period. loading the sector erase buffer may be done in any s equence, and the number of sectors may be from one sector to all sectors. the time between these additional cycl es must be less than t sea , otherwise erasure may begin. an y sector erase address and command following the exceeded time-out may or may not be accepted. it is recommended that processor interrupts be disabled during this time to ensure all commands are accepted. the interrupts can be re -enabled after the last sector erase command is written. note that the secured silicon sector , autoselect, and cfi fu nctions are unavailable wh en an erase operation in is progress. the syst em must rewrite the command sequence and an y additional addresses and commands. the system can determine the stat us of the erase operation by reading the ry/by# , status register or using data polling. refer to ready/busy# (ry/by#) on page 61 for information on ry/by#. refer to status register on page 36 for information on these status bits. refer to data polling status on page 37 for more information. once the sector erase operation has beg un, the status register read and eras e suspend commands are valid. all other commands are ignored. however, note that a hardware reset imm ediately terminates the erase oper ation and returns to read mode after t rph time. if a sector erase operation is terminated, the sector erase command sequence must be reinitiated once the device has reset operation to ensure data integrity. sector(s) protected by the asp dyb and ppb bits or password protection wil l not be erased. see asp on page 13 . if a sector is protected during multi-sector erase, sector erase will skip the pr otected sector and continue with next sector erase. the statu s register erase status bit and sector lock bit are not set to 1 by a failed erase on a protected sector. see embedded algorithm controller (eac) on page 19 for parameters and timing diagrams. sectors protected by the asp dyb and ppb bits will not be erased. see asp on page 13 .
document number: 002-00247 rev. *g page 31 of 105 s29gl01gt, s29gl512t figure 5.4 sector erase operation note: 1. see command summary for x8 bus cycles. no write unlock cycles (x16): address 555h, data aah address 2aah, data 55h write sector erase cycles (x16): address 555h, data 80h address 555h, data aah address 2aah, data 55h sector address, data 30h write additional sector addresses fail. write reset command to return to reading array. pass. device returns to reading array. perform write operation status algorithm select additional sectors? unlock cycle 1 unlock cycle 2 ye s ye s ye s ye s ye s no no no no last sector selected? done? erase error? command cycle 1 command cycle 2 command cycle 3 specify first sector for erasure error condition (exceeded timing limits) status may be obtained by reading status register, data polling, or rd/by# methods poll dq3. dq3 = 1? ? each additional cycle must be written within t sea timeout ? the host system may monitor status register dq7 or data polling dq3 or wait t sea to ensure acceptance of erase commands ? no limit on number of sectors ? commands other than erase suspend or selecting additional sectors for erasure during timeout reset device to reading array data
document number: 002-00247 rev. *g page 32 of 105 s29gl01gt, s29gl512t 5.4.8 erase suspend / erase resume the erase suspend command allows the system to interrupt a sector erase operation and then read data from, or program data to, the main flash array. this command is valid only during sector erase or program operation. the erase suspend command is ignored if written during the chip erase operation. when the erase suspend command is writ ten during the sector erase operation, the device requires a maximum of t esl (erase suspend latency) to suspend the erase operation and update the status bits. after the erase operation has been suspended, the part enters the erase-suspend mode. the system can read data from or program data to the main flash array. reading at any address within erase-suspended sectors produces und etermined data. the system can determine if a sector is actively erasing or is erase-suspended by read ing the status register or using data polling. refer to status register on page 36 for information on these status bits. refer to data polling status on page 37 for more information. after an erase-suspended program operation is complete, the eac returns to the erase-suspend state. the system can determine the status of the program op eration by reading the status register, ju st as in the standar d program operation. if a program failure occurs during erase suspend the status regist er clear or soft reset commands will return the device to the erase suspended state. erase will need to be resumed and completed before again trying to program the memory array. accesses and commands that are valid during erase suspend are: ? read to any other non-suspended sector ? program to any other non-suspended sector ? status register read ? status register clear ? erase resume command to resume the sector erase operation, the system must write the erase resume command. the device will revert to erasing and the status bits will be updated. furt her writes of the resume command are ignored. another erase suspend command can be written after the chip has resumed erasing. erase suspend and resume is not supported while entered in an aso. 5.4.9 aso entry and exit 5.4.9.1 id-cfi aso the system can access the id-cfi aso by issuing the id-cfi entry command seq uence during read m ode. see t he detail description table 7.3 on page 55 . the id-cfi aso allows th e following activities: ? read id-cfi aso, using the same sa as used in the entry command. ? read sector protection state at sector address (sa) + 2h. loca tion 2h provides volatile information on the current state of sec tor protection for the sector addressed. bit 0 of the word at loca tion 2h shows the logical nand of the ppb and dyb bits related to the addressed sector such that if the sector is protected by either the ppb=0 or the dyb=0 bit for that sector the state shown is protected. (1= sector protec ted, 0= sector unprotected.) ? aso exit. the following is a c source code example of usin g the cfi entry and exit functions. refer to the cypress low level driver user's guide for general information on cypress flash memory software development guidelines. /* example: cfi entry command */ *( (uint16 *)base_addr + 0x55 ) = 0x0098; /* write cfi entry command */ /* example: cfi exit command */ *( (uint16 *)base_addr + 0x000 ) = 0x00f0; /* write cfi exit command */
document number: 002-00247 rev. *g page 33 of 105 s29gl01gt, s29gl512t 5.4.9.2 status register aso the status register aso contains a single word of registered volatile status for embedded algorithms. when the status register read command is issued, the current status is captured (by the rising edge of we#) in to the register and the aso is entered. th e status register content app ears on all word locations. the first read access ex its the status register aso (with the rising edg e of ce# or oe#) and returns to the address space map in use wh en the status register read command was issued. write commands will not exit the status register aso state. 5.4.9.3 secure silicon region aso the system can access the secure silicon region by issuing th e secure silicon region entry command sequence during read mode. this entry command uses the sector address (sa) in the command to determine which sector will be overlaid. the secure silicon region aso allows the following activities: ? read secure silicon regions. ? program the customer secure silicon region is allowed using the word or write buffer programming commands. the unlock bypass commands and using acc is not allowed. ? aso exit using legacy secure silicon exit command for backward software compatibility. ? aso exit using the common exit command for all aso - alternative for a consistent exit method. the recommended procedure for using the ssr region 3 read password mode is as follows: ? program the data you want in ssr region 3. ? clear lock register bit 10 to 0, which disable further program operations. ? program the ssr region 3 password. ? clear lock register bit 11 to 0, which will enable the ssr r egion 3 password feature which requires that a password be applied before reading ssr region 3 is allowed. 5.4.9.4 lock register aso the system can access the lock register by issuing the lock register entry comma nd sequence during read mode. this entry command does not use a sector address from the entry command. the lock register appears at word location 0 in the device address space. all other locations in the device address space are undefined. the lock register aso allows the following activities: ? read lock register, using device address location 0. ? program the customer lock register usi ng a modified word programming command. ? aso exit using legacy command set exit command for backward software compatibility. ? aso exit using the common exit command for all aso ? alternative for a consistent exit method. 5.4.9.5 ecc status aso the system can access the ecc status aso by issuing the ec c status entry command sequenc e during read mode. the ecc status aso provides the enabled or disabled status of the ecc function for a specific page or if the ecc logic corrected a sing le bit error the selected page. the ecc status aso allows the following activities: ? read ecc status for the selected page.
document number: 002-00247 rev. *g page 34 of 105 s29gl01gt, s29gl512t 5.4.9.6 password aso the system can access the password aso by issuing the password ent ry command sequenc e during read mode. this entry command does not use a sector address from the entry command. the password appears at word locations 0 to 3 in the device address space. all other locations in the device address space are undefined. the password aso allows the following activities: ? read password, using device address location 0 to 3 (if not locked). ? program the password using a modified word programming command. ? unlock the ppb lock bit with the password unlock command. ? aso exit using legacy command set exit command for backward software compatibility. ? aso exit using the common exit command for all aso ? alternative for a consistent exit method. 5.4.9.7 ppb aso the system can access the ppb aso by issuing the ppb entry command sequence during read mode. this entry command does not use a sector address from the entry command. the ppb bit for a sector appears in bit 0 of all word locations in the sector. the ppb aso allows the following activities: ? read ppb protection status of a sector in bi t 0 of any word in the sector. ? program the ppb bit using a modi fied word programming command. ? erase all ppb bits wit h the ppb erase command. ? aso exit using legacy command set exit command for backward software compatibility. ? aso exit using the common exit command for all aso ? alternative for a consistent exit method. 5.4.9.8 ppb lock aso the system can access the ppb lock aso by issuing the ppb lock entry command sequence during read mode. this entry command does not use a sector address from the entry command. the global ppb lock bit appears in bit 0 of all word locations in the device. the ppb lock aso allows t he following activities: ? read ppb lock protection status in bit 0 of any word in the device address space. ? set the ppb lock bit using a modified word programming command. ? aso exit using legacy command set exit command for backward software compatibility. ? aso exit using the common exit command for all aso ? alternative for a consistent exit method. 5.4.9.9 dyb aso the system can access the dyb aso by issuing the dyb entry command sequence during read mode. this entry command does not use a sector address from the entry command. the dyb bit for a sector appears in bit 0 of all word locations in the sector. the dyb aso allows the following activities: ? read dyb protection status of a sector in bit 0 of any word in the sector. ? set the dyb bit using a modified word programming command. ? clear the dyb bit using a modified word programming command. ? aso exit using legacy command set exit command for backward software compatibility. ? aso exit using the common exit command for all aso ? alternative for a consistent exit method.
document number: 002-00247 rev. *g page 35 of 105 s29gl01gt, s29gl512t 5.4.9.10 software (command) reset / aso exit software reset is part of the command set (see table 7.1, command definitions x16 on page 48 ) that also returns the eac to standby state and must be used for the following conditions: ? exit aso modes ? clear timeout bit (dq5) for data polling when timeout occurs software reset does not affect ea mode. reset commands are ignored once programming or erasure has begun, until the operation is complete. software reset does not affect outputs; it serves pr imarily to return to read mode from an aso mode or f rom a failed program or erase operation. software reset may cause a return to read mode from undefined states that might result from invalid command sequences. however, a hardware reset may be required to return to normal operation from some undefined states. there is no software reset latency requiremen t. the reset command is executed during the t wph period. 5.4.9.11 continuity check feature the continuity check provides a basic test of connectivity from package connectors to each die pad and to each individual die i n a ddp. this feature is an extension of the legacy unlock cy cle sequence used at the beginning of several commands. the unlock sequence is two writes with alternating ones and zeros pattern on the lower portion of the addr ess and data lines with the patt ern inverted between the first and second write. to perform a continui ty check these patterns are extended to cover all address (am ax to 0) and data lines (dq15 to 0). a logic comparison circuit looks for the alternating one and zero pattern that is inverted be tween the two write cycles. in the case of a ddp the a26 input is used to select which die the writ es are sent to. when the corre ct patterns are detected t he status register bit zero is set to one. the status register clear command will clear the status register bit zero to a zero. the following table describes the continuity check sequence for a single die (e.g. gl01gt) in x16. the following table describes the continuity check sequence for a single die (e.g. gl01gt)in x8. phase access type address a26 address a25 to a0 data comment set-up write n/a xxxx555 xx71 clear die zero status write n/a 555 xx70 write status register read command to die zero read n/a x rd read status from die zero to confirm status bit zero = 0 continuity pattern write n/a 2aaaa55 ff00 first continuity cycle write n/a 15555aa 00ff second continuity cycle verify continuity pattern detected write n/a 555 xx70 write status register read command to die zero read n/a x rd read status from die zero to confirm status bit zero = 1 for continuity pattern detected phase access type address a26 address a25 to a-1 data comment set-up write n/a xxxx555 71 clear die zero status write n/a aaa 70 write status register read command to die zero read n/a x rd read status from die zero to confirm status bit zero = 0 continuity pattern write n/a 55554ab ff first continuity cycle write n/a 2aaab54 00 second continuity cycle verify continuity pattern detected write n/a 555 70 write status register read command to die zero read n/a x rd read status from die zero to confirm status bit zero = 1 for continuity pattern detected
document number: 002-00247 rev. *g page 36 of 105 s29gl01gt, s29gl512t 5.5 status monitoring there are three methods for monitoring ea status. previous generati ons of the s29gl flash family used the methods called data polling and ready/busy# (ry/by#) signal. t hese methods are still supported by the s29g l-t family. one additional method is reading the status register. 5.5.1 status register the status of program and erase operations is provided by a single 16-bit status regi ster. the status register read command is written followed by a read access of the status register information. when the status register read command is issued, the curr ent status is captured (by the rising edge of we#) into the register and the aso is entered. the contents of the status register is aliased (overlaid) the full memory address space. valid read (ce# and oe# low) access in the status r egister aso exits the aso (with th e rising edge of ce# or oe# for t ceph /t oeph time) and returns to the address space map in use when the status register read command was issued. while in x8 mode the fu ll status register can be read (both the u pper byte and lower byte) with one status register entry by keeping ce# and oe# low and having a transition on a-1. writ e operations are ignored and the device will stay in status register aso.the status register co ntains bits related to the results ? success or failure ? of the most recently comple ted embedded algorithms (ea): ? erase status (bit 5), ? program status (bit 4), ? write buffer abort (bit 3), ? sector locked status (bit 1), ? continuity check pattern detected (bit 0). and, bits related to the current state of any in process ea: ? device busy (bit 7), ? erase suspended (bit 6), ? program suspended (bit 2), the current state bits indicate whether an ea is in process, suspended, or completed. the upper 8 bits (bits 15:8) are reserved. these have undefined high or low value that can change from one status read to anoth er. these bits should be treated as don't care and ignored by any software reading status. the soft reset command will clear to 0 bits [5, 4, 1, 0] of the status register if status register bit 3 =0. it will not affect the current state bits. the clear status register command will clear to 0 bits [5, 4, 3, 1, 0] of the status register but will not affect the current s tate bits.
document number: 002-00247 rev. *g page 37 of 105 s29gl01gt, s29gl512t notes: 1. bits 15 thru 8 are reserved for future use and may display as 0 or 1. these bits should be ig nored (masked) when checking sta tus. 2. bit 7 is 1 when there is no embedded algorithm in progress in the device. 3. bits 6 thru 1 are valid only if bit 7 is 1. 4. all bits are put in their reset status by cold reset or warm reset. 5. bits 5, 4, 3, and 1 are cleared to 0 by the clear status register command or reset command. 6. upon issuing the erase suspend command, the user must continue to read status until drb becomes 1. 7. essb is cleared to 0 by the erase resume command. 8. esb reflects success or failure of the most recent erase operation. 9. psb reflects success or failure of the most recent program operation. 10. during erase suspend, programming to the suspended sector or a sector in the queue, will be ignored and no error reported. 11. upon issuing the program suspend command, the user must continue to read status until drb becomes 1. 12. pssb is cleared to 0 by the program resume command. 13. slsb indicates that a program or erase operation failed because the sector was locked. 14. slsb reflects the status of the most recent program or erase operation. 5.5.2 data polling status during an active embedded algorithm the eac switches to the data polling aso to display ea status to any read access. a single word of status information is aliased in all locations of the dev ice address space. in the status word there are several bits t o determine the status of an ea. these are referred to as dq bits as they appear on the data bus during a read access while an ea is in progress. dq bits 15 to 8, dq4, and dq0 are reserved and prov ide undefined data. status monito ring software must mask the reserved bits and treat them as don't care. in x8 mode a-1 is ignored when performing data polling. table 5.6 on page 40 and the following subsections describe the functions of the remaining bits. 5.5.2.1 dq7: data# polling the data# polling bit, dq7, indicates to the host system whether an embedded algorithm is in progress or has completed. data# polling is valid after the rising edge of the final we# pulse in the program or erase command sequence. note that the data# pol ling is valid only for the last word being programmed in the write- buffer-page during write buffer programming. reading data# pollin g status on any word other than the last word to be programmed in the write-buffer-page will return false status information. during the embedded program algorithm, the device outputs on dq7 t he complement of the data bit programmed to dq7. this dq7 status also applies to programming durin g erase suspend. when the embedded program al gorithm is complete, the device outputs the data bit programmed to bit 7 of the last word programmed. in case of a program suspend, the device allows only reading arra y data. if a program address falls within a protecte d sector, data# polling on dq7 is active for t dp , then the device returns to reading array data. during the embedded erase, evaluat e erase status, or blank che ck algorithms, data# polling produces a 0 on dq7. when the algorithm is complete, or if the device enters the erase suspend mode, data# polling produces a 1 on dq7. this is analogous to the complement / true datum output de scribed for the embedded program algorithm: the eras e function changes all the bits in a secto r to 1; prior to this, the device outputs the complement or '0'. the system must provide an addr ess within the sector selected fo r erasure to read valid status information on dq7. table 5.5 status register bit #15:876543210 bit description reserve d device ready bit erase suspend status bit erase status bit program status bit write buffer abort status bit program suspend status bit sector lock status bit continuity check bit name drb essb esb psb wbasb pssb slsb cc reset statusx10000000 busy status invalid 0 invalid invalid i nvalid invalid invalid invalid invalid ready status x 1 0=no erase in suspension 1=erase in suspension 0=erase successful 1=erase fail 0=program successful 1=program fail 0=program not aborted 1=program aborted during write to buffer command 0=no program in suspension 1=program in suspension 0=sector not locked during operation 1=sector locked error 0=continuity check pattern not detected 1=continuity check pattern detected
document number: 002-00247 rev. *g page 38 of 105 s29gl01gt, s29gl512t after an erase command sequence is written, if the sector selected for erasing is protec ted, data# polling on dq7 is active for t dp , then the device returns to reading array data. just prior to the completion of an embedded program or eras e operation, dq7 may change asyn chronously with dq6-dq0 while output enable (oe#) is asserted low. that is, the device may change from providing status information to valid data on dq7. depending on when the system samples the dq 7 output, it may read the status or valid data. even if the dev ice has completed the program or erase operation and dq7 has valid data, the data outputs on dq6-dq0 may be still invalid. valid data on dq7-d00 appears on successive read cycles. when the system detects dq7 has changed from the complement to true data, it can read valid data at dq15-dq0 (dq7-dq0 in x8 mode) on the following r ead cycles. this is because dq7 may change asynchron ously with dq6-dq0 while output enable (oe#) is asserted low. this is illustrated in figure 11.17 on page 87 . table 5.6 on page 40 shows the outputs for data# polling on dq7. figure 5.2 on page 24 shows the data# polling algorithm use in write buffer programming. valid dq7 data polling status may only be read from: ? the address of the last word loaded into the writ e buffer for a write buffer programming operation; ? the location of a single word programming operation; ? a location in a sector being erased, or evaluate erase status, or blank checked; ? or a location in any sector during chip erase. figure 5.5 data# polling algorithm note: 1. dq7 should be rechecked even if dq5 = 1 because dq7 may change simultaneously with dq5. 5.5.2.2 dq6: toggle bit i toggle bit i on dq6 indicates whether an embedded program or erase algorithm is in progress or complete, or whether the device has entered the program suspend or erase suspend mode. toggle bi t i may be read at any address, and is valid after the rising edge of the final we# pulse in the command sequenc e (prior to the progra m or erase operation). during an embedded program or erase algorit hm operation, successive read cycles to any address cause dq6 to toggle. (the system may use either oe# or ce# to control the read c ycles). when the operation is complete, dq6 stops toggling. after an erase command sequence is wri tten, if the sector selected for eras ing is protected, dq6 toggles for t dp , then the eac returns to standby (read mode). if the selected sector is not protected, the embedded erase al gorithm erases the unprotected sector. the system can use dq6 and dq2 together to determine whether a se ctor is actively erasing or er ase-suspended. when the device is actively erasing (that is, the embedded erase algorithm is in progress), dq6 toggles. when the device enters the program start read dq7 -dq0 - fail dq7 = data? no yes dq5 = 1? no yes dq7 = data? no yes pass read dq7 -dq0
document number: 002-00247 rev. *g page 39 of 105 s29gl01gt, s29gl512t suspend mode or erase suspend mode, dq6 stops toggling. howeve r, the system must also use dq2 to determine which sectors are erasing, or erase-suspended. alte rnatively, the system can use dq7 (see dq7: data# polling on page 37 ). dq6 also toggles during the erase-suspen d-program mode, and stops toggling once th e embedded program algorithm is complete. table 5.6 on page 40 shows the outputs for toggle bit i on dq6. figure 5.6 on page 40 shows the toggle bit algorithm in flowchart form, and the reading toggle bits dq6/dq2 on page 39 explains the algorithm. figure 5.6 on page 40 shows the toggle bit timing diagrams. see also dq2: toggle bit ii on page 39 . 5.5.2.3 dq3: sector erase timer after writing a sector erase command seque nce, the system may read dq3 to determine whether or not erasure has begun. see sector erase on page 30 for more details. (the sector erase timer does not apply to the chip erase command.) if additional sectors are selected for erasure, the entire time-out also applies afte r each additional sector erase co mmand. when the time-out period is complete, dq3 switches from a 0 to a 1. if the time between additional sector erase co mmands from the system can be assumed to be less than t sea , then the system need not monitor dq3. after the sector erase command is written, the system should read the status of dq7 (data# pollin g) or dq6 (toggle bit i) to en sure that the device has accepted the command s equence, and then read dq3. if dq3 is 1, the embedded erase algorithm has begun; all further commands (except erase suspend) are ignored until the erase operation is complete. if dq3 is 0, the device accepts additional sector erase commands. to ensure the command has b een accepted, the system software should check the status of dq3 prior to and following each sub-sequent sector erase command. if dq3 is high on t he second status check, the last command might not have been accepted. table 5.6 on page 40 shows the status of dq3 relative to the other status bits. 5.5.2.4 dq2: toggle bit ii toggle bit ii on dq2, when used with dq6, indicates whether a pa rticular sector is actively er asing (that is, the embedded eras e algorithm is in progress), or whether that sector is erase-su spended. toggle bit ii is valid after the rising edge of the final we# pulse in the command sequence. dq2 toggles when the system reads at addre sses within the sector selected for erasure (or all sectors selected for erase operat ion during multi-sector erase). (the system ma y use either oe# or ce# to control the re ad cycles). but dq2 cannot distinguish wheth er the sector is actively erasing or is erase-suspended. dq6, by comparison, indicate s whether the device is actively erasing, or is in erase suspend, but cannot distinguish if the sector is selected for erasure. thus, bo th status bits are required for sector and mode information. refer to table 5.6 on page 40 to compare outputs for dq2 and dq6. figure 5.5 on page 38 shows the toggle bit algorithm in flowchart form, and the reading toggle bits dq6/dq2 on page 39 explains the algorithm. see also figure 5.6 on page 40 shows the toggle bit timing diagram. 5.5.2.5 reading toggle bits dq6/dq2 refer to figure 5.5 on page 38 for the following discussion. whenever the system init ially begins reading toggle bit status, it must read dq7-dq0 at least twice in a row to determine whether a toggle bi t is toggling. typically, the system would no te and store the value of the toggle bit after t he first read. after the second re ad, the system would co mpare the new value of the toggle bit w ith the previous value. if the toggle bit is not toggling, the device has completed the prog ram or erases operation. the system can rea d array data on dq15-dq0 (dq7-dq0 in x8 mode) on the following read cycle. however, if after the initial two read cycles, the system det ermines that the toggle bit is still toggling, the system also sho uld note whether the value of dq5 is high (see dq5: exceeded timing limits on page 40 ). if it is, the system sh ould then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as dq5 went hig h. if the toggle bit is no longer toggling, the device has successfully completed the program or er ase operation. if it is still toggling, the device did not com plete the operation successfully, and the system must write the reset command to return to re ading array data. it is recommended that dat a read for polling purposes only be used for polling purposes. once toggling has stopped array data will be available on subseque nt reads. the remaining scenario is that the system in itially determines that the toggle bit is toggling and dq5 has not gone high. the s ystem may continue to monitor the toggle bit and dq5 through successive read cycles, determining the status as described in the previ ous paragraph. alternat ively, it may choose to per form other system tasks. in th is case, the system must st art at the beginning of the algorithm when it returns to determine the status of the operation (top of figure 5.6 on page 40 ).
document number: 002-00247 rev. *g page 40 of 105 s29gl01gt, s29gl512t figure 5.6 toggle bit program notes: 1. read toggle bit twice to determine whether or not it is toggling. see text. 2. recheck toggle bit because it may stop toggling as dq5 changes to 1. see text. 5.5.2.6 dq5: exceeded timing limits dq5 indicates whether the program or erase time has exceeded a sp ecified internal pulse count limit. under these conditions dq5 produces a 1. this is a failure condition that indicates the pr ogram or erase cycle was not succ essfully completed. the system must issue the reset command to return the device to reading array data. when a timeout occurs, the software must send a soft reset or st atus register reset command to clear the timeout bit (dq5) and to return the eac to the initia l state. in this case, it is possible that t he flash will continue to communicate busy for up to t tor after the reset command is sent. 5.5.2.7 dq1: write-to-buffer abort dq1 indicates whethe r a write-to-buffer operatio n was aborted. u nder these conditions dq1 produces a 1. t he system must issue the write-to-buffer-abort-reset command sequence or status regist er clear command to return the eac to standby (read mode) and the status register failed bits are cleared. see write buffer programming on page 23 for more details. table 5.6 data polling status operation dq7 (note 2) dq6 dq5 (note 1) dq3 dq2 (note 2) dq1 (note 4) ry/ by# standard mode embedded program algorithm dq7# toggle 0 n/a no toggle 0 0 reading within erasing sector (note 5) 0 toggle 0 1 toggle n/a 0 reading outside erasing sector (note 5) 0 toggle 0 1 no toggle n/a 0 program suspend mode (note 3) reading within program suspended sector invalid (not allowed) invalid (not allowed) invalid (not allowed) invalid (not allowed) invalid (not allowed) invalid (not allowed) 1 reading within non-program suspended sector data data data data data data 1 start read dq7 -dq0 (note 1) erase/program operation not complete toggle bit = toggle? yes no dq5 = 1? no yes read dq7 -dq0 twice (notes 1, 2) toggle bit = toggle? yes no erase/program operation complete read dq7 -dq0
document number: 002-00247 rev. *g page 41 of 105 s29gl01gt, s29gl512t notes: 1. dq5 switches to '1' when an embedded program or embedded erase operation has exceeded the maximum timing limits. see dq5: exceeded timing limits on page 40 for more information. 2. dq7 and dq2 require a valid address when reading status info rmation. refer to the appropriate subsection for further details. 3. data are invalid for addresses in a program suspended line. all addresses other than the program suspended line can be read f or valid data. 4. dq1 indicates the write-to-buffer abort status during write-buffer-programming operations. 5. dq3 = 0 for 50 s after last sector is loaded during a multi-sector erase. 6. applies only to program operations. 7. if secsi is over laid on a suspended sector, if a program operation is initiated while in the secsi mode, dq6 will toggle and dq2 will not toggle during the embedded operation. 5.6 error types and clearing procedures there are three types of errors reported by the embedded operati on status methods. depending on the error type, the status reported and procedure for clearing the error status is different. following is the clearing of error status: ? if an aso was entered before the error the device remains entered in the aso awaiting aso read or a command write. ? if an erase was suspended before the error the device return s to the erase suspended state awaiting flash array read or a command write. ? otherwise, the device will be in standby state aw aiting flash array read or a command write. 5.6.1 embedded op eration error if an error occurs during an embedded operation (program, erase, bl ank check, or password unlock) the device (eac) remains busy . the ry/by# output remains low, data polling status continues to be overlaid on all address locations, and the status register s hows ready with valid status bits. th e device remains busy until the error status is detected by the host system status monitoring a nd the error status is cleared. during embedded algorithm error status the da ta polling status will show the following: ? dq7 is the inversion of the dq7 bit in the last word loaded into the write buffer or last word of the password in the case of t he password unlock command. dq7 = 0 for an erase, evaluate erase status, blank check failure ? dq6 continues to toggle ? dq5 = 1; failure of the embedded operation ? dq4 is rfu and should be treated as don?t care (masked) ? dq3 = 1 to indicate an embedded sector erase was in prog ress or 0 to indicate an embedded program was in progress ? dq2 continues to toggle, independent of the address used to read status ? dq1 = 0; write buffer abort error ? dq0 is rfu and should be treated as don?t care (masked) erase suspend mode (note 7) reading within erase suspended sector 1 no toggle 0 n/a toggle n/a 1 reading within non-erase suspend sector data data data data data data 1 programming within non-erase suspended sector dq7# toggle 0 n/a n/a n/a 0 write-to- buffer (note 4) (note 6) busy state dq7# toggle 0 n/a no toggle 0 0 exceeded timing limits dq7# toggle 1 n/a n/a 0 0 abort state dq7# toggle 0 n/a n/a 1 0 table 5.6 data polling status (continued) operation dq7 (note 2) dq6 dq5 (note 1) dq3 dq2 (note 2) dq1 (note 4) ry/ by#
document number: 002-00247 rev. *g page 42 of 105 s29gl01gt, s29gl512t during embedded algorithm error status the status register will show the following: ? sr[7] = 1; valid status displayed ? sr[6] = x; may or may not be erase suspended during the ea error ? sr[5] = 1 on erase or blank check error; else = 0 ? sr[4] = 1 on program or password unlock error; else = 0 ? sr[3] = 0; write buffer abort ? sr[2] = 0; program suspended ? sr[1] = 0; protected sector ? sr[0] = x; rfu, treat as don?t care (masked) when the embedded algorithm error status is detected, it is necessary to clear the erro r status in order to return to normal op eration, with ry/by# high, ready for a new read or command write. the error status can be cleared by writing: ? reset command ? status register clear command commands that are accepted during em bedded algorithm error status are: ? status register read ? reset command ? status register clear command 5.6.2 protection error if an embedded algorithm attempts to change data within a protected area (program, or erase of a protected sector or otp area) the device (eac) goes busy for a period of t dp then returns to normal operation. during the busy period the ry/by# output remains low, data polling status continues to be overlaid on all address locations, and the st atus register shows not ready with invali d status bits (sr[7] = 0). during the protection error stat us busy period the data polling status will show the following: ? dq7 is the inversion of the dq7 bit in the last word loaded into the write buffer. dq7 = 0 for an erase failure ? dq6 continues to toggle, independent of the address used to read status ? dq5 = 0; to indicate no failure of the embedded operation during the busy period ? dq4 is rfu and should be treated as don?t care (masked) ? dq3 = 1 to indicate embedded sector erase in progress ? dq2 continues to toggle, independent of the address used to read status ? dq1 = 0; write buffer abort error ? dq0 is rfu and should be treated as don?t care (masked) commands that are accepted during the protection error status busy period are: ? status register read when the busy period ends the device returns to normal operation, the data polling status is no longer overlaid, ry/by# is high , and the status register shows ready with valid status bits. the device is ready fo r flash array read or write of a new command. after the protection error status busy period the status register will show the following: ? sr[7] = 1; valid status displayed ? sr[6] = x; may or may not be erase suspended after the protection error busy period ? sr[5] = 1 on erase error, else = 0 ? sr[4] = 1 on program error, else = 0
document number: 002-00247 rev. *g page 43 of 105 s29gl01gt, s29gl512t ? sr[3] = 0; program not aborted ? sr[2] = 0; no program in suspension ? sr[1] = 1; error due to attempting to change a protected location ? sr[0] = x; rfu, treat as don?t care (masked) commands that are accepted after the pr otection error status busy period are: ? any command 5.6.3 write buffer abort if an error occurs during a write to buffer command the device (eac) remains busy. the ry/by# output remains low, data polling status continues to be overlaid on all address locations, and t he status register shows ready wit h valid status bits. the devic e remains busy until the error status is det ected by the host system status monitoring and the error status is cleared. during write to buffer abort (wba) error status t he data polling status will show the following: ? dq7 is the inversion of the dq7 bit in th e last word loaded into the write buffer ? dq6 continues to toggle, independent of the address used to read status ? dq5 = 0; to indicate no failure of the programming operation. wba is an error in the values input by the write to buffer comman d before the programming operation can begin ? dq4 is rfu and should be treated as don?t care (masked) ? dq3 is don't care after program operation as no erase is in pr ogress. if the write buffer prog ram operation was started after a n erase operation had been suspended then dq3 = 1. if there was no erase operation in progress then dq3 is a don't care and should be masked. ? dq2 does not toggle after program operation as no erase is in progress. if the write buffer program operation was started after an erase operation had been suspended then dq2 will toggle in the sector where the erase oper ation was suspended and not in any other sector. if there was no erase operation in prog ress then dq2 is a don't care and should be masked. ? dq1 = 1: write buffer abort error ? dq0 is rfu and should be treated as don?t care (masked) during write to buffer abort (wba) error status the status register will show the following: ? sr[7] = 1; valid status displayed ? sr[6] = x; may or may not be erase suspended during the wba error status ? sr[5] = 0; erase successful ? sr[4] = 1; programming related error ? sr[3] = 1; write buffer abort ? sr[2] = 0; no program in suspension ? sr[1] = 0; sector not locked during operation ? sr[0] = x; rfu, treat as don?t care (masked) when the wba error status is detected, it is necessary to clear the error status in order to return to normal operation, with r y/by# high, ready for a new read or command write. the error status can be cleared and device returned to normal operation by writing : ? write buffer abort reset command ? status register clear command commands that are accepted during write to buffer abort (wba) error status are: ? status register read ? reads the status register and returns to wba busy state ? write buffer abort reset command ? status register clear command
document number: 002-00247 rev. *g page 44 of 105 s29gl01gt, s29gl512t 5.7 embedded algorithm performance table the joint electron device engineering council (jedec) standard j esd22-a117 defines the procedural requirements for performing valid endurance and retention tests based on a qualification specification. this methodology is intended to determine the abili ty of a flash device to sustain repeated data changes without failure (progr am/erase endurance) and to retain data for the expected lif e (data retention). endurance and retention qualification specif ications are specified in jesd47 or may be developed using knowledge-based methods as in jesd94. notes: 1. not 100% tested. 2. typical program and erase times assume the following conditions: 25c, 3.0v v cc , 10,000 cycle, and a random data pattern. 3. effective write buffer specification is ba sed upon a 512-byte write buffer operation. 4. 512-byte load is not supported in x8 mode. 5. in the pre-programming step of the embedded erase algorithm, all words are programmed to 0000h before sector and chip erasure . 6. system-level overhead is the time required to ex ecute the bus-cycle sequence for the program command. see table 7.1, command definitions x16 on page 48 for further information on command definitions. table 5.7 embedded algo rithm characteristics ( ? 40c to +85c) parameter min typ (note 2) max (note 3) unit comments sector erase time 128 kbyte 535 3500 ms includes pre-programming prior to erasure (note 7) chip erase gl512t 274 1792 (note 1) s gl01gt 548 3584 (note 1) s single word programming time (note 1) 160 750 s buffer programming time 2-byte (note 1) 160 750 s 32-byte (note 1) 195 750 64-byte (note 1) 219 750 128-byte (note 1) 258 750 256-byte (note 1) 327 750 512-byte (note 6) 451 750 effective write buffer program operation per word 512-byte 1.76 s sector programming time 128 kb (full buffer programming) 115.4 192 ms (note 8) erase suspend latency (t esl ) 40s program suspend latency (t psl ) 40s erase resume to next erase suspend (t ers ) 100 s minimum of 60 s but ? typical periods are needed for erase to progress to completion. program resume to next program suspend (t prs ) 100 s minimum of 60 s but ? typical periods are needed for program to progress to completion. evaluate erase status (t ees )25 30s blank check 6.2 8.5 ms nop (number of program-operations, per line) 256
document number: 002-00247 rev. *g page 45 of 105 s29gl01gt, s29gl512t notes: 1. not 100% tested. 2. typical program and erase times assume the following conditions: 25c, 3.0v v cc , 10,000 cycle, and a random data pattern. 3. effective write buffer specification is ba sed upon a 512-byte write buffer operation. 4. 512-byte load is not supported in x8 mode. 5. in the pre-programming step of the embedded erase algorithm, all words are programmed to 0000h before sector and chip erasure . 6. system-level overhead is the time required to ex ecute the bus-cycle sequence for the program command. see table 7.1, command definitions x16 on page 48 for further information on command definitions. table 5.8 embedded algo rithm characteristics ( ? 40 c to +105 c) parameter min typ (note 2) max (note 3) unit comments sector erase time 128 kbyte 535 3500 ms includes pre-programming prior to erasure (note 7) chip erase gl512t 274 1792 (note 1) s gl01gt 548 3584 (note 1) single word programming time (note 1) 160 1050 s buffer programming time 2-byte (note 1) 160 1050 s 32-byte (note 1) 195 1050 64-byte (note 1) 219 1050 128-byte (note 1) 258 1050 256-byte (note 1) 327 1050 512-byte (note 1) 451 1050 effective write buffer program operation per word 512-byte 1.76 s sector programming time 128 kb (full buffer programming) 115.4 269 ms (note 8) erase suspend latency (t esl ) 50s program suspend latency (t psl ) 50s erase resume to next erase suspend (t ers ) 100 s minimum of 60 ns but ? typical periods are needed for erase to progress to completion. program resume to next program suspend (t prs ) 100 s minimum of 60 ns but ? typical periods are needed for program to progress to completion. evaluate erase status (t ees )25 30s blank check 7.6 9.0 ms nop (number of program-operations, per line) 1 per 16 word
document number: 002-00247 rev. *g page 46 of 105 s29gl01gt, s29gl512t notes: 1. not 100% tested. 2. typical program and erase times assume the following condit ions: 25c, 3.0v vcc, 1,000 cycle, and a random data pattern. 3. effective write buffer specification is ba sed upon a 512-byte write buffer operation. 4. 512-byte load is not supported in x8 mode. 5. in the pre-programming step of the embedded erase algorithm, all words are programmed to 0000h before sector and chip erasure . 6. system-level overhead is the time required to ex ecute the bus-cycle sequence for the program command. see table 7.1, command definitions x16 on page 48 for further information on command definitions. table 5.9 embedded algo rithm characteristics ( ? 40 c to +125 c) parameter min typ (note 2) max (note 3) unit comments sector erase time 128 kbyte 535 3500 ms chip erase gl512t 274 1792 (note 1) s includes pre-programming prior to erasure (note 7) gl01gt 548 3584 (note 1) s single word programming time (note 1) 160 1050 s buffer programming time 2-byte (note 1) 160 1050 32-byte (note 1) 195 1050 64-byte (note 1) 219 1050 128-byte (note 1) 258 1050 256-byte (note 1) 327 1050 512-byte (note 1) 451 1050 effective write buffer program operation per word 512-byte 1.76 s sector programming time 128 kb (full buffer programming) 115.4 269 ms (note 8) erase suspend latency (tesl) 50 s program suspend latency (tpsl) 50 s erase resume to next erase suspend (ters) 100 s minimum of 60 ns but typical periods are needed for erase to progress to completion. program resume to next program suspend (tprs) 100 s minimum of 60 ns but typical periods are needed for program to progress to completion. evaluate erase status (tees) 25 30 s blank check 7.6 9.0 ms nop (number of program-operations, per line) 1 per 16 word
document number: 002-00247 rev. *g page 47 of 105 s29gl01gt, s29gl512t 6. data integrity 6.1 erase endurance note: 1. each write command to a non-volatile register causes a p/e cycl e on the entire non-volatile register array. otp bits and regi sters internally reside in a separate array that is not p/e cycled. 6.2 data retention contact cypress sales or an fae representative for additional in formation on the data integrity. an application note is availab le at www.cypress.com/appnotes . table 6.1 erase endurance parameter minimum unit program/erase cycles per main flash array sectors 100k p/e cycle program/erase cycles per ppb array or non-volatile register array 100k p/e cycle table 6.2 data retention parameter test conditions minimum time unit data retention time 1k program/erase cycles 20 years 10k program/erase cycles 2 years 100k program/erase cycles 0.2 years
document number: 002-00247 rev. *g page 48 of 105 s29gl01gt, s29gl512t 7. software interface reference 7.1 command summary table 7.1 command definitions x16 command sequence (note 1) cycles bus cycles (notes 2 - 5 ) first second third fourth fifth sixth seventh addr data addr data addr data addr data addr data addr data addr data read (note 6) 1 ra rd reset/aso exit (notes 7 , 18 )1xxxf0 status register read 2 555 70 xxx rd status register clear 1 555 71 word program 4 555 aa 2aa 55 555 a0 pa pd write to buffer 6 555 aa 2aa 55 sa 25 sa wc wbl pd wbl pd program buffer to flash (confirm) 1sa29 write-to-buffer-abort reset (note 13) 3 555 aa 2aa 55 555 f0 unlock bypass enter 3 555 aa 2aa 55 555 20 program (note 9) 2 xxx a0 pa pd write-to-buffer (note 9) 4 sa 25 sa wc wbl pd wbl pd program buffer to flash (confirm) 1sa29 write-to-buffer-abort reset (note 13) 3 555 aa 2aa 55 555 f0 sector erase (note 9) 2 xxx 80 sa 30 chip erase (note 9) 2 xxx 80 xxx 10 command set exit (note 10) 2 xxx 90 xxx 00 chip erase 6 555 aa 2aa 55 555 80 555 aa 2aa 55 555 10 sector erase (note 20) 6 555 aa 2aa 55 555 80 555 aa 2aa 55 sa 30 erase suspend/program suspend legacy method (note 11) 1 xxx b0 erase suspend enhanced method erase resume/program resume legacy method (note 12) 1xxx30 erase resume enhanced method program suspend enhanced method 1xxx51 program resume enhanced method 1xxx50 evaluate erase state 1 (sa) 555 35 blank check 1 (sa) 555 33 cfi enter (note 8) 1 (sa) 55 98 continuity check 7 555 71 555 70 xx rd 2aaa a55 ff00 15555 aa 00ff 555 70 xx rd
document number: 002-00247 rev. *g page 49 of 105 s29gl01gt, s29gl512t id-cfi (autoselect) aso id (autoselect) entry 3 555 aa 2aa 55 555 90 cfi enter (note 8) 15598 id-cfi read 1 ra rd cfi exit 1 xxx ff reset/aso exit (notes 7 , 18 ) 1xxxf0 secure silicon region command definitions secure silicon region (ssr) aso ssr entry 3 555 aa 2aa 55 (sa) 555 88 read (note 6) 1 ra rd word program 4 555 aa 2aa 55 555 a0 pa pd write to buffer 6 555 aa 2aa 55 sa 25 sa wc wbl pd wbl pd program buffer to flash (confirm) 1sa29 write-to-buffer-abort reset (note 13) 3 555 aa 2aa 55 555 f0 ssr exit (note 13) 4 555 aa 2aa 55 555 90 xx 0 reset/aso exit (notes 7 , 18 ) 1xxxf0 lock register command set definitions lock register aso lock register entry 3 555 aa 2aa 55 555 40 program (note 17) 2 xxx a0 xxx pd read (note 17) 1 0 rd command set exit (notes 14 , 18 ) 2 xxx 90 xxx 0 reset/aso exit (notes 7 , 18 ) 1xxxf0 password protection command set definitions password aso password aso entry 3 555 aa 2aa 55 555 60 program (note 16) 2 xxx a0 pwax pwdx read (note 15) 4 0 pwd0 1 pwd1 2 pwd2 3 pwd3 unlock (note 15) 7 0 25 0 3 0pwd01pwd12pwd23pwd30 29 command set exit (notes 14 , 18 ) 2 xxx 90 xxx 0 reset/aso exit (notes 7 , 18 ) 1xxxf0 non-volatile sector protection command set definitions ppb (non-volatile sector protection) ppb entry 3 555 aa 2aa 55 555 c0 ppb program (note 19) 2 xxx a0 sa 0 all ppb erase (note 19) 2xxx80030 ppb read (note 19) 1 sa rd (0) command set exit (notes 14 , 18 ) 2 xxx 90 xxx 0 reset/aso exit (notes 7 , 18 ) 1xxxf0 table 7.1 command definitions x16 (continued) command sequence (note 1) cycles bus cycles (notes 2 - 5 ) first second third fourth fifth sixth seventh addr data addr data addr data addr data addr data addr data addr data
document number: 002-00247 rev. *g page 50 of 105 s29gl01gt, s29gl512t legend: x = don't care. ra = address of the memory to be read. rd = data read from location ra during read operation. pa = address of the memory location to be programmed. pd = data to be programmed at location pa. sa = address of the sector selected. address bits amax-a16 uniquely select any sector. wbl = write buffer location. the address must be within the same line. wc = word count is the number of write buffer locations to load minus 1. pwax = ppb password address for word0 = 00h, word1 = 01h, word2 = 02h, and word3 = 03h. ssr3 password address for word0 = 10h, word1 = 11h, word2 = 12h, and word3 = 13h. pwdx = password data word0, word1, word2, and word3. gray vs. white box = read vs. write operation. notes: 1. see table 9.1, interface states on page 62 for description of bus operations. 2. all values are in hexadecimal. 3. except for the following, all bus cycles are write cycle: r ead cycle during re ad, id/cfi read (manufact uring id / device id), indicator bits, secure silicon region read, ssr lock read, and 2nd cycle of status register read. 4. data bits dq15-dq8 are don't care in command sequences, except for rd, pd, wc and pwd. 5. address bits amax -a11 are don't cares for unlock and command cycles, unless sa or pa required. ( amax is the highest address pin.). 6. no unlock or command cycles required when reading array data. 7. the reset command is required to return to reading array data when device is in the aso mode, or if dq5 goes high (while the device is providing status data). 8. command is valid when device is ready to read array data. 9. the unlock-bypass command is required prior to the unlock-bypass-program and the unlock bypass write to buffer commands. 10. the unlock-bypass-reset command is required to return to r eading array data when the device is in the unlock bypass mode. 11. the system can read and program/program suspend in non-erasing sectors, or enter the id-cfi aso, when in the erase suspend m ode. the erase suspend command is valid only during a sector erase operation. global non-volatile sector protecti on freeze command set definitions ppb lock bit ppb lock entry 3 555 aa 2aa 55 555 50 ppb lock bit cleared 2 xxx a0 xxx 0 ppb lock status read (note 19) 1 xxx rd (0) command set exit (notes 14 , 18 ) 2 xxx 90 xxx 0 reset/aso exit (note 18) 1xxxf0 volatile sector protecti on command set definitions dyb (volatile sector protection) aso dyb aso entry 3 555 aa 2aa 55 555 e0 dyb set (note 19) 2 xxx a0 sa 0 dyb clear (note 19) 2 xxx a0 sa 1 dyb status read (note 19) 1 sa rd (0) command set exit (notes 14 , 18 ) 2 xxx 90 xxx 0 reset/aso exit (note 18) 1xxxf0 command set definitions ecc ecc aso ecc aso entry 3 555 aa 2aa 55 555 75 ecc status read 1 ra rd command set exit (notes 14 , 18 ) 2xxxf0 table 7.1 command definitions x16 (continued) command sequence (note 1) cycles bus cycles (notes 2 - 5 ) first second third fourth fifth sixth seventh addr data addr data addr data addr data addr data addr data addr data
document number: 002-00247 rev. *g page 51 of 105 s29gl01gt, s29gl512t 12. the erase resume/program resume command is valid only during the erase suspend/program suspend modes. 13. issue this command sequence to return to read state after detecti ng device is in a write-to-buffer-abort state. important: t he full command sequence is required if resetting out of abort. 14. the exit command returns the device to reading the array. 15. the password portion can be entered or read in any order as l ong as the entire 64-bit password is entered or read. addresses are 10h-13h if the ssr3 is being accessed. 16. for pwdx, only one portion of the password can be programmed per each a0 command. portions of the password must be programme d in sequential order (pwd0 - pwd3). 17. all lock register bits are one-time programmable. the program state = 0 and the erase state = 1. also, both the persistent p rotection mode lock bit and the password protection mode lock bit cannot be progr ammed at the same time or the lock register bits program oper ation halts and returns the device to read state. lock register bits that are reserved for future use are undefined and may be 0?s or 1's. 18. if any of the entry commands was issued, an exit command must be issued to reset the device into read state. 19. protected state = 00h, unprotected state = 01h. the sector address for dyb set, dyb clear, or ppb program command may be any location within the sector - the lower order bits of the sector address are don't care. 20. see section 5.4.7.2, sector erase on page 30 for description of multi-sector erase. table 7.2 command definitions x8 command sequence (note 1) cycles bus cycles (notes 2 - 5 ) first second third fourth fifth sixth seventh addr data addr data addr data addr data addr data addr data addr data read (note 5) 1 ra rd reset/aso exit (notes 6 , 17 )1xxxf0 status register read 2 aaa 70 xxx rd status register clear 1 aaa 71 word program 4 aaa aa 555 55 aaa a0 pa pd write to buffer (note 19) 6 aaa aa 555 55 sa 25 sa wc wbl pd wbl pd program buffer to flash (confirm) 1 sa 29 write-to-buffer-abort reset (note 12) 3 aaa aa 555 55 aaa f0 unlock bypass enter 3 aaa aa 555 55 aaa 20 program (note 8) 2 xxx a0 pa pd write-to-buffer (note 8) 4 sa 25 sa wc wbl pd wbl pd program buffer to flash (confirm) (note 8) 1sa 29 write-to-buffer-abort reset (note 12) 3 aaa aa 555 55 aaa f0 sector erase (note 8) 2 xxx 80 sa 30 chip erase (note 8) 2 xxx 80 xxx 10 command set exit (note 9) 2 xxx 90 xxx 00 chip erase 6 aaa aa 555 55 aaa 80 aaa aa 555 55 aaa 10 sector erase (note 19) 6 aaa aa 555 55 aaa 80 aaa aa 555 55 sa 30 erase suspend/program suspend legacy method (note 10) 1 xxx b0 erase suspend enhanced method erase resume/program resume legacy method (note 11) 1xxx 30 erase resume enhanced method program suspend enhanced method 1xxx 51 program resume enhanced method 1xxx 50 evaluate erase state 1 (sa) aaa 35 blank check 1 (sa) aaa 33
document number: 002-00247 rev. *g page 52 of 105 s29gl01gt, s29gl512t cfi enter (note 7) 1 (sa) aa 98 continuity check 7 aaa 71 aaa 70 xx rd 55554 ab ff 2aaa b54 00 aaa 70 xx rd id-cfi (autoselect) aso id (autoselect) entry 3 aaa aa 555 55 aaa 90 cfi enter (note 7) 1aa 98 id-cfi read 1 ra rd cfi exit 1 xxx ff reset/aso exit (notes 6 , 17 ) 1xxx f0 secure silicon region command definitions secure silicon region (ssr) aso ssr entry 3 aaa aa 555 55 (sa) aaa 88 read (note 5) 1 ra rd word program 4 aaa aa 555 55 aaa a0 pa pd write to buffer (note 19) 6 aaa aa 555 55 sa 25 sa wc wbl pd wbl pd program buffer to flash (confirm) 1sa29 write-to-buffer-abort reset (note 12) 3 aaa aa 555 55 aaa f0 ssr exit (note 12) 4 aaa aa 555 55 aaa 90 xx 0 reset/aso exit (notes 6 , 17 ) 1xxx f0 lock register command set definitions lock register aso lock register entry 3 aaa aa 555 55 aaa 40 program (note 16) 2 xxx a0 xxx pd read (note 16) 1 0 rd command set exit (notes 13 , 17 ) 2 xxx 90 xxx 0 reset/aso exit (notes 6 , 17 ) 1xxx f0 password protection command set definitions password aso password aso entry 3 aaa aa 555 55 aaa 60 program (note 15) 2 xxx a0 pwax pwdx read (note 14) 8 0 pwd0 1 pwd1 2 pwd2 3 pwd3 4 pwd4 5 pwd5 6 pwd6 7 pwd7 unlock (note 14) 11 0 25 0 3 0pwd01pwd12pwd23pwd34pwd4 5pwd56pwd67pwd70 29 command set exit (notes 13 , 17 ) 2 xxx 90 xxx 0 reset/aso exit (notes 6 , 17 ) 1xxx f0 table 7.2 command definitions x8 (continued) command sequence (note 1) cycles bus cycles (notes 2 - 5 ) first second third fourth fifth sixth seventh addr data addr data addr data addr data addr data addr data addr data
document number: 002-00247 rev. *g page 53 of 105 s29gl01gt, s29gl512t legend: x = don't care. ra = address of the memory to be read. rd = data read from location ra during read operation. pa = address of the memory location to be programmed. pd = data to be programmed at location pa. sa = address of the sector selected. address bits amax-a16 uniquely select any sector. wbl = write buffer location. the address must be within the same line. wc = word count is the number of write buffer locations to load minus 1. pwax = ppb password address for byte0 = 00h, byte1 = 01h, byt e2 = 02h, byte3 = 03h, byte04= 04h, byte5 = 05h, byte6 = 06h, and byte7 = 07h. ssr3 password address for byte0 = 20h, byte1 = 21h, byte2 = 22h, byte3 = 23h, byte04= 24h, byte5 = 25h, byte6 = 26h, and byte7 = 27h. pwdx = password data byte0, byte1, byte2, byte3, byte4, byte5, byte6, and byte7 gray vs. white box = read vs. write operation. notes: 1. see table 9.1, interface states on page 62 for description of bus operations. 2. all values are in hexadecimal. non-volatile sector protection command set definitions ppb (non-volatile sector protection) ppb entry 3 aaa aa 555 55 aaa c0 ppb program (note 18) 2 xxx a0 sa 0 all ppb erase (note 18) 2xxx 80 0 30 ppb read (note 18) 1 sa rd (0) command set exit (notes 13 , 17 ) 2 xxx 90 xxx 0 reset/aso exit (notes 6 , 17 ) 1xxx f0 global non-volatile sector protecti on freeze command set definitions ppb lock bit ppb lock entry 3 aaa aa 555 55 aaa 50 ppb lock bit cleared 2 xxx a0 xxx 0 ppb lock status read (note 18) 1 xxx rd (0) command set exit (notes 13 , 17 ) 2 xxx 90 xxx 0 reset/aso exit (note 17) 1xxx f0 volatile sector protection command set definitions dyb (volatile sector protection) aso dyb aso entry 3 aaa aa 555 55 aaa e0 dyb set (note 18) 2 xxx a0 sa 0 dyb clear (note 18) 2 xxx a0 sa 1 dyb status read (note 18) 1 sa rd (0) command set exit (notes 13 , 17 ) 2 xxx 90 xxx 0 reset/aso exit (note 17) 1xxx f0 ecc command set definitions ecc aso ecc aso entry 3 aaa aa 555 55 aaa 75 ecc status read 1 ra rd command set exit (notes 14 , 18 ) 2xxxf0 table 7.2 command definitions x8 (continued) command sequence (note 1) cycles bus cycles (notes 2 - 5 ) first second third fourth fifth sixth seventh addr data addr data addr data addr data addr data addr data addr data
document number: 002-00247 rev. *g page 54 of 105 s29gl01gt, s29gl512t 3. except for the following, all bus cycles are write cycle: r ead cycle during re ad, id/cfi read (manufact uring id / device id), indicator bits, secure silicon region read, ssr lock read, and 2nd cycle of status register read . 4. address bits amax -a11 are don't cares for unlock and command cycles, unless sa or pa required. ( amax is the highest address pin.). 5. no unlock or command cycles required when reading array data. 6. the reset command is required to return to reading array data when device is in the aso mode, or if dq5 goes high (while the device is providing status data). 7. command is valid when device is ready to read array data. 8. the unlock-bypass command is required prior to the unlock-bypass-program command and the unlock bypass write to buffer comman ds. 9. the unlock-bypass-reset command is required to return to r eading array data when the device is in the unlock bypass mode. 10. the system can read and program/program suspend in non-erasing sectors, or enter the id-cfi aso, when in the erase suspend m ode. the erase suspend command is valid only during a sector erase operation. 11. the erase resume/program resume command is valid only during the erase suspend/program suspend modes. 12. issue this command sequence to return to read state after detecti ng device is in a write-to-buffer-abort state. important: t he full command sequence is required if resetting out of abort. 13. the exit command returns the device to reading the array. 14. the password portion can be entered or read in any order as l ong as the entire 64-bit password is entered or read. addresses are 20h-27h if the ssr3 is being accessed. 15. for pwdx, only one portion of the password can be programmed per each a0 command. portions of the password must be programme d in sequential order (pwd0 - pwd7). 16. all lock register bits are one-time programmable. the program state = 0 and the erase state = 1. also, both the persistent p rotection mode lock bit and the password protection mode lock bit cannot be progr ammed at the same time or the lock register bits program oper ation aborts and returns the device to read state. lock register bits that are reserved for future use are undefined and may be 0?s o r 1's. 17. if any of the entry commands was issued, an exit command must be issued to reset the device into read state. 18. protected state = 00h, unprotected state = 01h. the sector address for dyb set, dyb clear, or ppb program command may be any location within the sector - the lower order bits of the sector address are don't care. 19. see section 5.4.7.2, sector erase on page 30 for description of multi-sector erase. 20. in x8 mode the wc represents 2 x8 wbl/pd cycles (e.g. if wc = 0, then 5th bus cycle would load data to lower byte address a- 1 = low and 6th bus cycle would load data to upper byte address a-1 = high).
document number: 002-00247 rev. *g page 55 of 105 s29gl01gt, s29gl512t 7.2 device id and common flas h interface (id- cfi) aso map the device id portion of the aso (word locations 0h to 0fh) pr ovides manufacturer id, device id , sector protection state, and b asic feature set information for the device. the access time to read location 02h is always t acc and a read of this location requires ce# to go high before the read and return low to initiate the read (asynchronous read access). page mode read between location 02h and other id locations is not supporte d. page mode read between id locations other than 02h is supported. in x8 mode, address a-1 is ignored and the lower 8 bits of data will be returned for both address, in cfi only. while in x8 onl y cfi or only autoselect data can be read. in x16 mode, able to read both memories from either command. for additional information see id-cfi aso on page 32 . table 7.3 id (autoselect) address map description address (x16) address (x8) read data manufacture id (sa) + 0000h (sa) + 0000h 0001h device id (sa) + 0001h (sa) + 0002h 227eh protection verification (sa) + 0002h (sa) + 0004h sector protection state (1= sector protected, 0= sector unprotected). to read a different sa protection state only a new sa needs to be given. indicator bits (sa) + 0003h (sa) + 0006h dq15-dq08 = 1 (reserved) dq7 - factory locked secure silicon region 1 = locked, 0 = not locked dq6 - customer locked secure silicon region 1 = locked 0 = not locked dq5 = 1 (reserved) dq4 - wp# protects 0 = lowest address sector 1 = highest address sector dq3 - dq0 = 1 (reserved) rfu (sa) + 0004h (sa) + 0008h reserved (sa) + 0005h (sa) + 000ah reserved (sa) + 0006h (sa) + 000ch reserved (sa) + 0007h (sa) + 000eh reserved (sa) + 0008h (sa) + 0010h reserved (sa) + 0009h (sa) + 0012h reserved (sa) + 000ah (sa) + 0014h reserved (sa) + 000bh (sa) + 0016h reserved lower software bits (sa) + 000ch (sa) + 0018h bit 0 - status register support 1 = status register supported 0 = status register not supported bit 1 - dq polling support 1 = dq bits polling supported 0 = dq bits polling not supported bit 3-2 - command set support 11 = reserved 10 = reserved 01 = reduced command set 00 = classic command set bits 4-15 - reserved = 0 upper software bits (sa) + 000dh (sa) + 001ah reserved device id (sa) + 000eh (sa) + 001ch 2228h = 1 gb 2223h = 512 mb device id (sa) + 000fh (sa) + 001eh 2201h
document number: 002-00247 rev. *g page 56 of 105 s29gl01gt, s29gl512t table 7.4 cfi query identification string word address byte address data description (sa) + 0010h (sa) + 0011h (sa) + 0012h (sa) + 0020h (sa) + 0022h (sa) + 0024h 0051h 0052h 0059h query unique ascii string ?qry? (sa) + 0013h (sa) + 0014h (sa) + 0026h (sa) + 0028h 0002h 0000h primary oem command set (sa) + 0015h (sa) + 0016h (sa) + 002ah (sa) + 002ch 0040h 0000h address for primary extended table (sa) + 0017h (sa) + 0018h (sa) + 002eh (sa) + 0030h 0000h 0000h alternate oem command set (00h = none exists) (sa) + 0019h (sa) + 001ah (sa) + 0032h (sa) + 0034h 0000h 0000h address for alternate oem extended table (00h = none exists) table 7.5 cfi system interface string word address byte address data description (sa) + 001bh (sa) + 0036h 0027h v cc min. (erase/program) (d7-d4: volts, d3-d0: 100 mv) (sa) + 001ch (sa) + 0038h 0036h v cc max. (erase/program) (d7-d4: volts, d3-d0: 100 mv) (sa) + 001dh (sa) + 003ah 0000h v pp min. voltage (00h = no v pp pin present) (sa) + 001eh (sa) + 003ch 0000h v pp max. voltage (00h = no v pp pin present) (sa) + 001fh (sa) + 003eh 0008h typical timeout per single word write 2 n s (sa) + 0020h (sa) + 0040h 0009h typical timeout for max multi-byte program, 2 n s (00h = not supported) (sa) + 0021h (sa) + 0042h 000ah typical timeout per individual block erase 2 n ms (sa) + 0022h (sa) + 0044h 0014h (1 gb) 0013h (512 mb) typical timeout for full chip erase 2 n ms (00h = not supported) (sa) + 0023h (sa) + 0046h 0002h (85c) 0003h (105c) max. timeout for single word write 2 n times typical (sa) + 0024h (sa) + 0048h 0001h (85c) 0002h (105c) max. timeout for buffer write 2 n times typical (sa) + 0025h (sa) + 004ah 0002h max. timeout per individual block erase 2 n times typical (sa) + 0026h (sa) + 004ch 0002h max. timeout for full chip erase 2 n times typical (00h = not supported)
document number: 002-00247 rev. *g page 57 of 105 s29gl01gt, s29gl512t table 7.6 cfi device geometry definition word address byte address data description (sa) + 0027h (sa) + 004eh 001bh (1 gb) 001ah (512 mb) device size = 2 n byte; (sa) + 0028h (sa) + 0050h 0002h flash device interface description 0 = x8-only, 1 = x16-only, 2 = x8/x16 capable (sa) + 0029h (sa) + 0052h 0000h (sa) + 002ah (sa) + 0054h 0009h max. number of byte in multi-byte write = 2 n (00 = not supported) (sa) + 002bh (sa) + 0056h 0000h (sa) + 002ch (sa) + 0058h 0001h number of erase block regions within device 1 = uniform device, 2 = boot device (sa) + 002dh (sa) + 005ah 00xxh erase block region 1 information (refer to jedec jesd68-01 or jep137 specifications) 00ffh, 0003h, 0000h, 0002h =1 gb 00ffh, 0001h, 0000h, 0002h = 512 mb (sa) + 002eh (sa) + 005ch 000xh (sa) + 002fh (sa) + 005eh 0000h (sa) + 0030h (sa) + 0060h 000xh (sa) + 0031h (sa) + 0062h 0000h erase block region 2 information (refer to cfi publication 100) (sa) + 0032h (sa) + 0064h 0000h (sa) + 0033h (sa) + 0066h 0000h (sa) + 0034h (sa) + 0068h 0000h (sa) + 0035h (sa) + 006ah 0000h erase block region 3 information (refer to cfi publication 100) (sa) + 0036h (sa) + 006ch 0000h (sa) + 0037h (sa) + 006eh 0000h (sa) + 0038h (sa) + 0070h 0000h (sa) + 0039h (sa) + 0072h 0000h erase block region 4 information (refer to cfi publication 100) (sa) + 003ah (sa) + 0074h 0000h (sa) + 003bh (sa) + 0076h 0000h (sa) + 003ch (sa) + 0078h 0000h (sa) + 003dh (sa) + 007ah ffffh reserved (sa) + 003eh (sa) + 007ch ffffh (sa) + 003fh (sa) + 007eh ffffh
document number: 002-00247 rev. *g page 58 of 105 s29gl01gt, s29gl512t table 7.7 cfi primary vendor-specific extended query word address byte address data description (sa) + 0040h (sa) + 0080h 0050h query-unique ascii string ?pri? (sa) + 0041h (sa) + 0082h 0052h (sa) + 0042h (sa) + 0084h 0049h (sa) + 0043h (sa) + 0086h 0031h major version number, ascii (sa) + 0044h (sa) + 0088h 0033h (cfi 1.3) 0035h (cfi 1.5) minor version number, ascii 0033h = cfi minor version 3 (model numbers 03, 04, v3, and v4) 0035h = cfi minor version 5 (model number is 01, 02, v1, and v2) (sa) + 0045h (sa) + 008ah 0024h address sensitive unlock (bits 1-0) 00b = required 01b = not required process technology (bits 5-2) 0000b = 0.23 m floating gate 0001b = 0.17 m floating gate 0010b = 0.23 m mirrorbit 0011b = 0.13 m floating gate 0100b = 0.11 m mirrorbit 0101b = 0.09 m mirrorbit 0110b = 0.09 m floating gate 0111b = 0.065 m mirrorbit eclipse 1000b = 0.065 m mirrorbit 1001b = 0.045 m mirrorbit (sa) + 0046h (sa) + 008ch 0002h erase suspend 0 = not supported 1 = read only 2 = read and write (sa) + 0047h (sa) + 008eh 0001h sector protect 00 = not supported x = number of sector s in smallest group (sa) + 0048h (sa) + 0090h 0000h temporary sector unprotect 00 = not supported 01 = supported (sa) + 0049h (sa) + 0092h 0008h sector protect/unprotect scheme 04 = high voltage method 05 = software command locking method 08 = advanced sector protection method (sa) + 004ah (sa) + 0094h 0000h simultaneous operation 00 = not supported x = number of banks (sa) + 004bh (sa) + 0096h 0000h burst mode type 00 = not supported 01 = supported (sa) + 004ch (sa) + 0098h 0003h page mode type 00 = not supported 01 = 4 word page 02 = 8 word page 03 =16 word page (sa) + 004dh (sa) + 009ah 00b5h acc (acceleration) supply minimum 00 = not supported d7-d4: volt d3-d0: 100 mv (sa) + 004eh (sa) + 009ch 00c5h acc (acceleration) supply maximum 00 = not supported d7-d4: volt d3-d0: 100 mv
document number: 002-00247 rev. *g page 59 of 105 s29gl01gt, s29gl512t (sa) + 004fh (sa) + 009eh 0004h (bottom) 0005h (top) wp# protection 00h = flash device without wp protect (no boot) 01h = eight 8 kb sectors at top and bottom with wp (dual boot) 02h = bottom boot device with wp protect (bottom boot) 03h = top boot device with wp protect (top boot) 04h = uniform, bottom wp protect (uniform bottom boot) 05h = uniform, top wp protect (uniform top boot) 06h = wp protect for all sectors 07h = uniform, top and bottom wp protect (sa) + 0050h (sa) + 00a0h 0001h program suspend 00 = not supported 01 = supported below queries only available for cfi version 1.5 (sa) +0051h (sa) +00a2h 0001h unlock bypass 00 = not supported 01 = supported (sa) + 0052h (sa) + 00a4h 0009h secured silicon sector (customer otp area) size 2 n (bytes) (sa) + 0053h (sa) + 00a6h 008fh software features bit 0: status register polling (1 = supported, 0 = not supported) bit 1: dq polling (1 = supported, 0 = not supported) b it 2 : ne w p r og r a m su sp en d /r e su m e co m m an d s ( 1 = su pp o r te d , 0 = no t su pp o r te d ) bit 3: word programming (1 = supported, 0 = not supported) bit 4: bit-field programming (1 = supported, 0 = not supported) bit 5: autodetect programming (1 = supported, 0 = not supported) bit 6: rfu bit 7: multiple writes per line (1 = supported, 0 = not supported) (sa) + 0054h (sa) + 00a8h 0005h page size = 2 n bytes (sa) + 0055h (sa) + 00aah 0006h erase suspend timeout maximum < 2 n (s) (sa) + 0056h (sa) + 00ach 0006h program suspend timeout maximum < 2 n (s) (sa) + 0057h to (sa) + 0077h (sa) + 00aeh to (sa) + 00ach ffffh reserved (sa) + 0078h (sa) + 00f0h 0006h embedded hardware reset timeout maximum < 2 n (s) reset with reset pin (sa) + 0079h (sa) + 00f2h 0009h non-embedded hardware reset timeout maximum < 2 n (s) power on reset table 7.7 cfi primary vendor-specific extended query (continued) word address byte address data description
document number: 002-00247 rev. *g page 60 of 105 s29gl01gt, s29gl512t hardware interface 8. signal descriptions 8.1 address and data configuration address and data are connected in parallel (adp) via separate signal inputs and i/os. 8.2 input/output summary table 8.1 i/o summary symbol type description reset# input hardware reset. at v il , causes the device to reset control logic to its standby state, ready for reading array data. ce# input chip enable. at v il , selects the device for data transfer with the host memory controller. oe# input output enable. at v il , causes outputs to be actively driven. at v ih , causes outputs to be high impedance (high-z). we# input write enable. at v il , indicates data transfer from host to device. at v ih , indicates data transfer is from device to host. amax-a0 input address inputs. a25-a0 for s29gl01gt a24-a0 for s29gl512t dq14-dq0 input/output data inputs and outputs dq15/a-1 input/output dq15: data inputs and outputs a-1: lsb address input in byte mode wp#/acc input write protect. at v il , disables program and erase functions in the lowest or highest address 64-kword (128-kb) sector of the device. at v ih , the sector is not protected. at v hh , automatically places device in unlock bypass mode. wp# has an internal pull up; when unconnected wp# is at v ih . ry/by# output ? open drain ready/busy. indicates whether an embedded algorithm is in progress or complete. at v il , the device is actively engaged in an embedded algorithm such as erasing or programming. at high-z, the device is ready for read or a new command write - requires external pull-up resistor to detect the high-z state. multiple devices may have their ry/by# outputs tied together to detect when all devices are ready. byte# input selects data bus width. at v il , the device is in byte configuration and dat a i/o pins dq7-dq0 are active and dq15/a-1 becomes the lsb address input. at v ih , the device is in word configuration an d data i/o pins dq15-dq0 are active. v cc power supply core power supply v io power supply versatile i/o power supply. v ss power supply power supplies ground nc no connect not connected internally. the pin/ball location may be used in printed circuit board (pcb) as part of a routing cha nnel. rfu no connect reserved for future use. not currently connected internally but the pin/ball location should be left unconnected and unused by pcb routing channel for future compatibility. the pin/ball may be used by a signal in the future. dnu reserved do not use. reserved for use by cypress. the pin/ball is connected internally. the input has an internal pull down resistance to v ss . the pin/ball can be left open or tied to v ss on the pcb.
document number: 002-00247 rev. *g page 61 of 105 s29gl01gt, s29gl512t 8.3 word/byte configuration the byte# pin controls whether the device data i/o pins operate in the byte or word configuration. if the byte# pin is set at l ogic 1, the device is in word configuration, dq0- dq15 are active and controlled by ce# and oe#. if the byte# pin is set at logic 0, the devic e is in byte configuration, and only dat a i/o pins dq0-dq7 are active and controll ed by ce# and oe#. the data i/o pins dq8-dq14 ar e tri-stated, and the dq15 pin is used as an input for the lsb (a-1) address function . the byte# pin can only be switch while the device is in standby (read mode). the byte# pin has an internal pul l-up. though not requir ed in a x16 only system, the pin s hould be connected to high (e.g. v io ) 8.4 versatile i/o feature the maximum output voltage level driven by, and input le vels acceptable to, the device are determined by the v io power supply. this supply allows the device to drive and receive signals to and from other devices on the same bus having interface signal le vels different from the device core voltage. 8.5 ready/busy# (ry/by#) ry/by# is a dedicated, open drai n output pin that indicates whether an embedded al gorithm, power-on reset (por), or hardware reset is in progress or complete. the ry/ by# status is valid after the rising edge of the final we# pulse in a command sequence , when v cc is above v cc minimum during por, or after the falling edge of reset #. since ry/by# is an open drain output, several ry/by# pins can be tied together in parallel with a pull up resistor to v io . if the output is low (busy), the device is actively erasing, pr ogramming, or resetting. (this in cludes programming in the erase suspend mode). if the output is high (ready), the device is ready to read data (including during the erase suspend mode), or is in the standby mode. table 5.6, data polling status on page 40 shows the outputs for ry /by# in each operation. if an embedded algorithm has failed (program / erase fa ilure as result of max pulses or program abort), ry/by# will stay low (busy) until status register bits 4 and 5 are cleared and t he reset command is issued. if an embedded algorithm has failed (sector is locked), ry/by# will return high (ready). this includes erase or programming on a locked sector . 8.6 hardware reset the reset# input provides a hardwar e method of resett ing the device to standby st ate. when reset# is dr iven low for at least a period of t rp , the device immediately: ? terminates any operation in progress, ? exits any aso, ? tristates all outputs, ? resets the status register, ? resets the eac to standby state. ? ce# is ignored for the duration of the reset operation (t rph ). ? to meet the reset current specification (i cc5 ) ce# must be held high. to ensure data integrity any operation that was interrupted should be reinitiated once the device is ready to accept another command sequence.
document number: 002-00247 rev. *g page 62 of 105 s29gl01gt, s29gl512t 9. signal protocols the following sections describe t he host system interface signal behavior and timing for the 29 gl-t family flash devices. 9.1 interface states table 9.1 describes the required value of each in terface signal for each interface state. legend: l = v il h = v ih x = either v il or v ih l/h = rising edge h/l = falling edge valid = all bus signals have stable l or h level modified = valid state different from a previous valid state available = read data is internally stored with output driver controlled by oe# notes: 1. address are amax:a0 in word mode; amax:a-1 in byte mode. 2. we# and oe# can not be at v il at the same time. 3. read with output disable is a read initiated with oe# high. 4. automatic sleep is a read/write operation where data has been driven on the bus for an extended period, without ce# going hig h and the device internal logic has gone into standby mode to conserve power. 5. if wp# = v il , on the outermost sector remains protected. if wp# = v ih , the outermost sector is unprotected. wp# has an internal pull-up; when unconnected, wp# is at v ih . 6. v il = v ss and v ih = v io. table 9.1 interface states interface state v cc v io reset# ce# oe# we# byte# (note 6) wp#/ acc amax-a0 (note 1) dq0-dq7 dq8-dq15 byte# = v ih byte = v il power-off with hardware data protection < v lko ? v cc xxxx l or h x x high-z high-z high-z power-on (cold) reset ? v cc min ? v io min ? v cc xxxx l or h x x high-z high-z high-z hardware (warm) reset ? v cc min ? v io min ? v cc lxxx l or h x x high-z high-z high-z interface standby ? v cc min ? v io min ? v cc hhxx l or h h x high-z high-z high-z automatic sleep (notes 2 , 4 ) ? v cc min ? v io min ? v cc hlxx l or h h valid output available output available dq8-dq14 = high-z, dq15 = a-1 read with output disable (note 3) ? v cc min ? v io min ? v cc hlhh l or h x valid high-z high-z high-z random read ? v cc min ? v io min h l l h x valid output valid output valid dq8-dq14 = high-z, dq15 = a-1 page read ? v cc min ? v io min ? v cc hllh l or h x amax-a4 valid a3-a0 (or a3-a-1) modified output valid output valid dq8-dq14 = high-z, dq15 = a-1 write ? v cc min ? v io min ? v cc hlhl l or h (note 5) valid input valid input valid dq8-dq14 = high-z, dq15 = a-1
document number: 002-00247 rev. *g page 63 of 105 s29gl01gt, s29gl512t 9.2 power-off with hardware data protection the memory is considered to be powered off when the core power supply (v cc ) drops below the lock-out voltage (v lko ). when v cc is below v lko , the entire memory array is protected against a program or erase operation. this ensures that no spurious alteration of the memory content can occur during power transition. during a power supply transition down to power-off, v io should remain less than or equal to v cc . if v cc goes below v rst (min) then returns above v rst (min) to v cc minimum, the power-on reset in terface state is entered and the eac starts the cold reset embedded algorithm. 9.3 power conservation modes 9.3.1 interface standby standby is the default, low power, state for the interface while the device is not selected by the host for data transfer (ce# = high). all inputs are ignored in this state and all outputs except ry/ by# are high impedance. ry/by# is a direct output of the eac, no t controlled by the host interface. 9.3.2 automatic sleep the automatic sleep mode reduces device interf ace energy consumption to the sleep level (i cc6 ) following the completion of a random read access time. the device automatically enables this mode when addresses remain stable for t acc + 30 ns. while in automatic sleep mode, output data is latch ed and always available to the system. output of the data depends on the level of the oe# signal but, the automatic sleep mode cu rrent is independent of the oe# signal level. standard address access timings (t acc or t pacc ) provide new data when addresses are changed. refer the dc characteristics on page 68 for the automatic sleep mode current specification i cc6 . automatic sleep helps reduce current consum ption especially when the host system clo ck is slowed for power reduction. during slow system clock periods, read and write cycles may extend many times their length versus when the system is operating at high speed. even though ce# may be low throughout these extended data transfer cycles, the memory device host interface will go to the automatic sleep current at t acc + 30 ns. the device will remain at the automatic sleep current for t assb . then the device will transition to the standby current level. this keeps the memory at the automatic sleep or standby power level for most of the lo ng duration data transfer cycles, rather than consuming full read pow er all the time that the memory device is selected by the hos t system. however, the eac operates independent of t he automatic sleep mode of the host interfac e and will continue to draw current durin g an active embedded algorithm. only when both the host interface and eac are in their standby stat es is the standby level curren t achieved. 9.4 read 9.4.1 read with output disable when the ce# signal is asserted low, the host system memory contro ller begins a read or write da ta transfer. often there is a p eriod at the beginning of a data transfer when ce# is low, address is valid, oe# is high, and we# is high. during this state a read a ccess is assumed and the random read process is started while the data outputs remain at high impedance. if the oe# signal goes low, the interface transitions to the random read state, with data outpu ts actively driven. if the we# si gnal is asserted low, the i nterface transitions to the write state. note, oe# and we# should never be low at the same time to ensure no data bus contention between the host system and memory. 9.4.2 random (asynchronous) read when the host system interf ace selects the memory device by driving ce# low, the device interface leaves the standby state. if we# is high when ce# goes low, a random read access is star ted. the data output depends on the address map mode and the address provided at the time the read access is started.
document number: 002-00247 rev. *g page 64 of 105 s29gl01gt, s29gl512t the data appears on dq15-dq0 (dq7-dq0 in x8 mode) when ce# is low, oe# is low, we# remains high, address remains stable, and the asynchronous access times are satisfied. address access time (t acc ) is equal to the delay from stable addresses to valid output data. the chip enable access time (t ce ) is the delay from stable ce# to valid data at the outputs. in order for the read data to be driven on to the data outputs the oe# signal must be low at least the output enable time (t oe ) before valid data is available. at the completion of the random access time from ce# active (t ce ), address stable (t acc ), or oe# active (t oe ), whichever occurs latest, the data outputs will provide valid read data from the cu rrently active address map mode. if ce# remains low and any of the amax to a4 address signals change to a new value, a new random read access begins. if ce# remains low and oe# goes high the interface transitions to the read with output disable state. if ce# remains low, oe# goes high, and we# goes low, the interface transitions to the write state. if ce# retu rns high, the interface goes to the standby state. back to back accesses, in which c e# remains low between accesses, requires an address change to initiate the second access. see asynchronous read operations on page 75 . 9.4.3 page read after a random read access is completed, if ce# remains low, oe # remains low, the amax to a4 address signals remain stable, and any of the a3 to a0 address signals change, a new access withi n the same page begins. in x8 mode, when any of the a3 to a- 1 address signals change, a new access within the same page begins. the page read completes much faster (t pacc ) than a random read access. 9.5 write 9.5.1 asynchronous write when we# goes low after ce is low, there is a transition from o ne of the read states to the write state. if we# is low before c e# goes low, there is a transition from t he standby state directly to the writ e state without beginning a read access. when ce# is low, oe# is high, and we# goes low, a write data transfer begins. note, oe# and we# should never be low at the same time to ensure no data bus contention between the host system and memory. when the asynchronous write cycle timing requirements are met the we# can go high to capture the address and data values in to eac command memory. address is captured by the falling edge of we # or ce#, whichever occurs later. data is captured by the rising edge of we# or ce #, whichever occurs earlier. when ce# is low before we# goes low and stays low after we# goes high, the access is called a we# controlled write. when we# is high and ce# goes high, there is a transition to the st andby state. if ce# remains low and we# goes high, there is a transition to the read with output disable state. when we# is low before ce# goes low and remains low after ce # goes high, the access is called a ce# controlled write. a ce# controlled write transitions to the standby state. if we# is low before ce# goes low, the write transfer is started by ce# going low. if we# is low after ce# goes high, the addre ss and data are captured by the rising edge of ce#. these cases are referred to as ce# contro lled write state transitions. write followed by read accesses, in which ce# remains low be tween accesses, requires an address change to initiate the following read access. back to back accesses, in which ce# remains low between accesse s, requires an address change to initiate the second access. the eac command memory array is not readable by the host system and has no aso. the eac examines the address and data in each write transfer to determine if the wr ite is part of a legal command sequence. wh en a legal command sequence is complete th e eac will initiate the appropriate ea. 9.5.2 write pulse ?glitch? protection noise pulses of less than 5 ns (typical ) on we# will not initiate a write cycle. 9.5.3 logical inhibit write cycles are inhibited by holding oe# at v il , or ce# at v ih , or we# at v ih . to initiate a write cycle, ce# and we# must be low (v il ) while oe# is high (v ih ).
document number: 002-00247 rev. *g page 65 of 105 s29gl01gt, s29gl512t 10. electrical specifications 10.1 absolute maximum ratings notes: 1. minimum dc voltage on input or i/o pins is -0.5v. during voltage transitions, input or i/o pins may undershoot v ss to -2.0v for periods of up to 20 ns. see figure 10.3 on page 67 . maximum dc voltage on input or i/o pins is v cc +0.5v. during voltage transitions, input or i/o pins may overshoot to v cc +2.0v for periods up to 20 ns. see figure 10.4 on page 68 . 2. no more than one output may be shorted to ground at a time. duration of the short circuit should not be greater than one seco nd. 3. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions abov e those indicated in the operational sections of this data sheet is not implied. ex posure of the device to absolute maximum rating conditions for extended periods may affect device reliability. 10.2 thermal resistance 10.3 latchup characteristics this product complies with jedec standar d jesd78c latchup testing requirements. table 10.1 absolute maximum ratings storage temperature plastic packages ? 65c to +150c ambient temperature with power applied ? 65c to +125c voltage with respect to ground all pins other than reset# (note 1) ? 0.5v to (v io + 0.5v) reset# (note 1) ? 0.5v to (v cc + 0.5v) output short circuit current (note 2) 100 ma v cc ? 0.5v to +4.0v v io ? 0.5v to +4.0v acc ? 0.5v to +12.5v table 10.2 thermal resistance parameter description lae064 ts056 laa064 vbu056 unit theta ja thermal resistance (junction to ambient) 39 84 39 39 c/w
document number: 002-00247 rev. *g page 66 of 105 s29gl01gt, s29gl512t 10.4 operating ranges 10.4.1 temperature ranges 10.4.2 power supply voltages note: 1. operating ranges define those limits between which the functionality of the device is guaranteed. 10.4.3 power-up and power-down during power-up or power-down v cc must always be greater than or equal to v io (v cc ? v io ). the device ignores all inputs until a time delay of t vcs has elapsed after the moment that v cc and v io both rise above, and stay above, the minimum v cc and v io thresholds. during t vcs the device is performing power on reset operations. during power-down or voltage drops below v cc lockout maximum (v lko ), the v cc and v io voltages must drop below v cc reset (v rst ) minimum for a period of t pd for the part to initialize correctly when v cc and v io again rise to their operating ranges. see figure 10.2 on page 67 . if during a voltage drop the v cc stays above v lko maximum the part will stay initialized and will work correctly when v cc is again above v cc minimum. if the part locks up from improper initialization, a hardware reset c an be used to initialize the part correctly. normal precautions must be taken for supply decoupling to stabilize the v cc and v io power supplies. each device in a system should have the v cc and v io power supplies decoupled by a suitable capacitor cl ose to the package connections (this capacitor is generally on the order of 0. 1 f). at no time should v io be greater then 200 mv above v cc (v cc ? v io - 200 mv). note: 1. not 100% tested. parameter symbol devices spec unit min max ambient temperature t a industrial (i) ? 40 +85 c industrial plus (v) ? 40 +105 extended (n) ? 40 +125 automotive, aec-q100 grade 3 (a) ? 40 +85 automotive, aec-q100 grade 2 (b) ? 40 +105 v cc 2.7v to 3.6v v io 1.65v to v cc + 200 mv table 10.3 power-up/power-down voltage and timing symbol parameter min max unit v cc v cc power supply 2.7 3.6 v v lko v cc level below which re-initialization is required (note 1) 2.5 v v rst v cc and v io low voltage needed to ensure initialization will occur (note 1) 1.0 v t vcs v cc and v io ? minimum to first access (note 1) 300 s t pd duration of v cc ? v rst (min) (note 1) 15 s
document number: 002-00247 rev. *g page 67 of 105 s29gl01gt, s29gl512t figure 10.1 power-up figure 10.2 power-down and voltage drop 10.4.4 input signal overshoot figure 10.3 maximum negative overshoot waveform vcc (m a x) vcc (m in) power supply voltage tim e t vcs full device access vcc v io (m in) v io (m a x) v io v cc (max) v cc (min) v cc and v io tim e v rst (min) t pd t vcs no device access allowed full device access allowed v lko (max) 20 ns 20 n s 20 ns -2.0v v max il v min il
document number: 002-00247 rev. *g page 68 of 105 s29gl01gt, s29gl512t figure 10.4 maximum positive overshoot waveform 10.5 dc characteristics notes: 1. i cc active while embedded algorithm is in progress. 2. not 100% tested. 3. automatic sleep mode enables the lower power mode when addresses remain stable for the specified designated time. 4. v io = 1.65v to v cc or 2.7v to v cc depending on the model. 5. v cc = 3v and v io = 3v or 1.8v. when v io is at 1.8v, i/o pins cannot operate at >1.8v. 6. during power-up there are spikes of current demand, the system needs to be able to supply this current to insure the part ini tializes correctly. 7. if an embedded operation is in progress at the start of reset, the current consumption will remain at the embedded operation specification until the embedded operation is stopped by the reset. if no embedded operation is in progress when reset is started, or following the stopping of an embedde d operation, i cc5 will be drawn during the remainder of t rph . after the end of t rph the device will go to standby mode until the next read or write. 8. the recommended pull-up resistor for ry/by# output is 5k to 10k ohms. table 10.4 dc characteristics ( ? 40c to +85c) parameter description test conditions min typ (note 2) max unit i li input load current v in = v ss to v cc , v cc = v cc max all others 0.02 1.0 a wp#, byte# 0.5 2.0 i lo output leakage current v out = v ss to v cc , v cc = v cc max 0.02 1.0 a i cc1 v cc active read current ce# = v il , oe# = v ih , address switching@ 5 mhz, v cc = v cc max 55 60 ma i cc2 v cc intra-page read current ce# = v il , oe# = v ih , address switching@ 33 mhz, v cc = v cc max 925ma i cc3 v cc active erase/program current (1) (2) ce# = v il , oe# = v ih , v cc = v cc max 45 100 ma i cc4 v cc standby current ce#, reset#, oe# = v ih , v ih = v io v il = v ss , v cc = v cc max 70 100 a i cc5 v cc reset current (2) (7) ce# = v ih , reset# = v il , v cc = v cc max 10 20 ma i cc6 automatic sleep mode (3) v ih = v io , v il = v ss v cc = v cc max, t acc + 30 ns 36ma v ih = v io , v il = v ss , v cc = v cc max, t assb 100 150 a i cc7 v cc current during power up (2) (6) reset# = v io, ce# = v io , oe# = v io , v cc = v cc max, 53 80 ma v il input low voltage (4) -0.5 0.3 x v io v v ih input high voltage (4) 0.7 x v io v io + 0.4 v v hh voltage for acc program acceleration v cc = 2.7 - 3.6 v 11.5 12.5 v v ol output low voltage (4) (8) i ol = 100 a for dq15-dq0; i ol = 2 ma for ry/by# 0.15 x v io v v oh output high voltage (4) i oh = 100 a 0.85 x v io v v lko low v cc lock-out voltage (2) 2.25 2.5 v v rst low v cc power on reset voltage (2) 1.0 v 20 ns 20 ns 20 ns v io + 2.0 v v max ih v min ih
document number: 002-00247 rev. *g page 69 of 105 s29gl01gt, s29gl512t notes: 1. i cc active while embedded algorithm is in progress. 2. not 100% tested. 3. automatic sleep mode enables the lower power mode when addresses remain stable for the specified designated time. 4. v io = 1.65v to v cc or 2.7v to v cc depending on the model. 5. v cc = 3v and v io = 3v or 1.8v. when v io is at 1.8v, i/o pins cannot operate at >1.8v. 6. during power-up there are spikes of current demand, the system needs to be able to supply this current to insure the part ini tializes correctly. 7. if an embedded operation is in progress at the start of reset, the current consumption will remain at the embedded operation specification until the embedded operation is stopped by the reset. if no embedded operation is in progress when reset is started, or following the stopping of an embedde d operation, i cc7 will be drawn during the remainder of t rph . after the end of t rph the device will go to standby mode until the next read or write. 8. the recommended pull-up resistor for ry/by# output is 5k to 10k ohms. table 10.5 dc characteristics ( ? 40c to +105c) parameter description test conditions min typ (note 2) max unit i li input load current v in = v ss to v cc , v cc = v cc max all others 0.02 1.0 a wp#, byte# 0.5 2.0 i lo output leakage current v out = v ss to v cc , v cc = v cc max 0.02 1.0 a i cc1 v cc active read current ce# = v il , oe# = v ih , address switching@ 5 mhz, v cc = v cc max 55 60 ma i cc2 v cc intra-page read current ce# = v il , oe# = v ih , address switching@ 33 mhz, v cc = v cc max 925ma i cc3 v cc active erase/program current (1) (2) ce# = v il , oe# = v ih , v cc = v cc max 45 100 ma i cc4 v cc standby current ce#, reset#, oe# = v ih , v ih = v io v il = v ss , v cc = v cc max 70 200 a i cc5 v cc reset current (2) (7) ce# = v ih , reset# = v il , v cc = v cc max 10 20 ma i cc6 automatic sleep mode (3) v ih = v io , v il = v ss v cc = v cc max, t acc + 30 ns 36ma v ih = v io , v il = v ss , v cc = v cc max, t assb 100 200 a i cc7 v cc current during power up (2) (6) reset# = v io, ce# = v io , oe# = v io , v cc = v cc max, 53 80 ma v il input low voltage (4) -0.5 0.3 x v io v v ih input high voltage (4) 0.7 x v io v io + 0.4 v v hh voltage for acc program acceleration v cc = 2.7 - 3.6 v 11.5 12.5 v v ol output low voltage (4) (8) i ol = 100 a for dq15-dq0; i ol = 2 ma for ry/by# 0.15 x v io v v oh output high voltage (4) i oh = 100 a 0.85 x v io v v lko low v cc lock-out voltage (2) 2.25 2.5 v v rst low v cc power on reset voltage (2) 1.0 v
document number: 002-00247 rev. *g page 70 of 105 s29gl01gt, s29gl512t notes: 1. icc active while embedded algorithm is in progress. 2. not 100% tested. 3. automatic sleep mode enables the lower power mode when addresses remain stable for the specified designated time. 4. vio = 1.65v to vcc or 2.7v to vcc depending on the model. 5. vcc = 3v and vio = 3v or 1.8v. when vio is at 1.8v, i/o pins cannot operate at >1.8v. 6. during power-up there are spikes of current demand, the system needs to be able to supply this current to insure the part ini tializes correctly. 7. if an embedded operation is in progress at the start of reset, the current consumption will remain at the embedded operation specification until the embedded operation is stopped by the reset. if no embedded operation is in progress when reset is started, or following the stopping of an embedde d operation, icc7 will be drawn during the remainder of trph. after the end of trph the device will go to standby mode until the next read or write. 8. the recommended pull-up resistor for ry/by# output is 5k to 10k ohms. table 10.6 dc characteristics (-40c to +125c) parameter description test conditions min typ (note 2) max unit i li input load current v in = v ss to v cc , v cc = v cc max all others 0.02 1.0 a wp#, byte# 0.5 2.0 i lo output leakage current v out = v ss to v cc , v cc = v cc max 0.02 1.0 a i cc1 v cc active read current ce# = v il , oe# = v ih , address switching@ 5 mhz, v cc = v cc max 55 60 ma i cc2 v cc intra-page read current ce# = v il , oe# = v ih , address switching@ 33 mhz, v cc = v cc max 925ma i cc3 v cc active erase/program current (1) (2) ce# = v il , oe# = v ih , v cc = v cc max 45 100 ma i cc4 v cc standby current ce#, reset#, oe# = v ih , v ih = v io v il = v ss , v cc = v cc max 70 215 a i cc5 v cc reset current (2) (7) ce# = v ih , reset# = v il , v cc = v cc max 10 20 ma i cc6 automatic sleep mode (3) v ih = v io , v il = v ss v cc = v cc max, t acc + 30 ns 36ma v ih = v io , v il = v ss , v cc = v cc max, t assb 100 215 a i cc7 v cc current during power up (2) (6) reset# = v io, ce# = v io , oe# = v io , v cc = v cc max, 53 80 ma v il input low voltage (4) 0.3 x v io v v ih input high voltage (4) v io + 0.4 v v hh voltage for acc program acceleration v cc = 2.7 - 3.6 v 12.5 v v ol output low voltage (4) (8) i ol = 100 a for dq15-dq0; i ol = 2 ma for ry/by# 0.15 x v io v v oh output high voltage (4) i oh = 100 a v v lko low v cc lock-out voltage (2) 2.5 v v rst low v cc power on reset voltage (2) 1.0 v
document number: 002-00247 rev. *g page 71 of 105 s29gl01gt, s29gl512t 10.6 capacitance characteristics notes: 1. sampled, not 100% tested. 2. test conditions t a = 25c, f = 1.0 mhz. notes: 1. sampled, not 100% tested. 2. test conditions t a = 25c, f = 1.0 mhz. notes: 1. sampled, not 100% tested. 2. test conditions t a = 25c, f = 1.0 mhz. notes: 1. sampled, not 100% tested. 2. test conditions t a = 25c, f = 1.0 mhz. table 10.7 connector capacitance for fbga (laa) package parameter symbol parameter description test setup typ max unit c in input capacitance v in = 0 4 5.5 pf c out output capacitance v out = 0 3.5 5 pf c in2 control pin capacitance v in = 0 4 8 pf ry/by# output capacitance v out = 0 3 4 pf reset# reset input capacitance v in = 0 21 23 pf table 10.8 connector capacitance for fbga (lae) package parameter symbol parameter description test setup typ max unit c in input capacitance v in = 0 3.5 5 pf c out output capacitance v out = 0 3.5 5 pf c in2 control pin capacitance v in = 0 3.5 7 pf ry/by# output capacitance v out = 0 2.5 3.5 pf reset# reset input capacitance v in = 0 20 22 pf table 10.9 connector capacitance for fbga (vbu) package parameter symbol parameter description test setup typ max unit c in input capacitance v in = 0 3.5 5 pf c out output capacitance v out = 0 3.5 5 pf c in2 control pin capacitance v in = 0 3.5 7 pf ry/by# output capacitance v out = 0 3 4 pf reset# reset input capacitance v in = 0 20 22 pf table 10.10 connector capacitance for tsop package parameter symbol parameter description test setup typ max unit c in input capacitance v in = 0 3 5 pf c out output capacitance v out = 0 3 4.5 pf c in2 control pin capacitance v in = 0 3.5 7 pf ry/by# output capacitance v out = 0 2.5 3.5 pf reset# reset input capacitance v in = 0 20 22 pf
document number: 002-00247 rev. *g page 72 of 105 s29gl01gt, s29gl512t 11. timing specifications 11.1 key to switching waveforms 11.2 ac test conditions figure 11.1 test setup note: 1. measured between v il max and v ih min. figure 11.2 input waveforms and measurement levels waveform inputs outputs steady changing from h to l changing from l to h don't care, any change permitted changing, state unknown does not apply center line is high impedance state (high-z) table 11.1 test specification parameter all speeds units output load capacitance, c l 30 pf input rise and fall times (note 1) 1.5 ns input pulse levels 0.0-v io v input timing measurement reference levels v io /2 v output timing measurement reference levels v io /2 v c l device under te s t v io 0.0 v 0.5 v io 0.5 v io output measurement level input
document number: 002-00247 rev. *g page 73 of 105 s29gl01gt, s29gl512t 11.3 power-on reset (por) and warm reset normal precautions must be taken for supply decoupling to stabilize the v cc and v io power supplies. each device in a system should have the v cc and v io power supplies decoupled by a suitable capacitor cl ose to the package connections (this capacitor is generally on the order of 0.1 f). notes: 1. not 100% tested. 2. timing measured from v cc reaching v cc minimum and v io reaching v io minimum to v ih on reset and v il on ce#. 3. reset# low is optional during por. if reset is asserted during por, the later of t rph , t vios , or t vcs will determine when ce# may go low. if reset# remains low after t vios , or t vcs is satisfied, t rph is measured from the end of t vios , or t vcs . reset must also be high t rh before ce# goes low. 4. v cc ? v io - 200 mv during power-up. 5. v cc and v io ramp rate can be non-linear. 6. sum of t rp and t rh must be equal to or greater than t rph. 11.3.1 power-on (cold) reset (por) during the rise of power supplies the v io supply voltage must remain less than or equal to the v cc supply voltage. v ih also must remain less than or equal to the v io supply. the cold reset embedded algorithm requires a relatively long, hundreds of s, period (t vcs ) to load all of the eac algorithms and default state from non-volatile memory. during the cold reset period all control signals including ce# and reset# are ignored. if ce# is low during t vcs the device may draw higher than normal por current during t vcs but the level of ce# will not affect the cold reset ea. reset# may be high or low during t vcs . if reset# is low during t vcs it may remain low at the end of t vcs to hold the device in the hardware reset state. if reset# is high at the end of t vcs the device will go to the standby state. when power is first applied, with supply voltage below v rst then rising to reach operating range minimum, internal device configuration and warm reset activities are initiated. ce# is ignored for the duration of the por operation (t vcs or t vios ). reset# low during this por period is optional. if reset# is driven low during por it must satisfy the hardware reset parameters t rp and t rph . in which case the reset operations will be completed at the later of t vcs or t vios or t rph . a ce#, oe#, or address transition will initiate the 1st read operation. if ce# is held low during por than the current add ress will be automatically read. during cold reset the device will draw i cc7 current. table 11.2 power on and reset parameters parameter description limit value unit t vcs v cc setup time to first access (1) (2) min 300 s t vios v io setup time to first access (1) (2) min 300 s t rph reset# low to ce# low min 35 s t rp reset# pulse width min 200 ns t rh time between reset# (high) and ce# (low) min 50 ns t ceh ce# pulse width high min 20 ns
document number: 002-00247 rev. *g page 74 of 105 s29gl01gt, s29gl512t figure 11.3 power-up diagram 11.3.2 hardware (warm) reset during hardware reset (t rph ) the device will draw i cc5 current. when reset# continue s to be held at v ss , the device draws cmos standby current (i cc4 ). if reset# is held at v il , but not at v ss , the standby current is greater. if a cold reset has not been completed by t he device when reset# is asserted low after t vcs , the cold reset# ea will be performed instead of the warm reset#, requiring t vcs time to complete. see figure 11.4, hardware reset on page 74 . after the device has completed por and entere d the standby state, any later transition to the hardware reset state will initiat e the warm reset embedded algorithm. a warm reset is much shorter than a co ld reset, taking tens of s (t rph ) to complete. during the warm reset ea, any in progress embedded algorithm is stoppe d and the eac is returned to it s por state without reloading eac algorithms from non-volatile memory. after the warm reset ea completes, the interface will remain in the hardware reset state if reset# remains low. when reset# returns high the interfac e will transit to the standby st ate. if reset# is high at the end of the warm reset ea, the interface will directly transit to the standby state. if ce# is held low during warm reset than t he current address will be automatically read. if por has not been properly completed by the end of t vcs , a later transition to the hardware reset state will cause a transition to the power-on reset interface state and initiate the cold reset embedded algorithm. this ensures the device can complete a cold reset even if some aspect of the system power-on voltage ramp -up causes the por to not initiate or complete correctly. the ry/ by# pin is low during cold or warm reset as an indication that the device is busy performing reset operations. hardware reset is initiated by the reset# signal going to v il . figure 11.4 hardware reset vcc vio reset# ce# trh tvios tvcs tceh reset# ce# trp trph trh tceh
document number: 002-00247 rev. *g page 75 of 105 s29gl01gt, s29gl512t 11.4 ac characteristics 11.4.1 asynchronous read operations note: 1. not 100% tested. table 11.3 read operation v io = v cc = 2.7 v to 3.6 v ( ? 40c to +85c) parameter description test setup speed option unit jedec std 100 t avav t rc read cycle time (note 1) 512 mb, 1 gb min 100 ns t avqv t acc address to output delay ce# = v il oe# = v il 512 mb, 1 gb max 100 ns t elqv t ce chip enable to output delay oe# = v il 512 mb, 1 gb max 100 ns t pacc page access time 512 mb, 1 gb max 15 ns t glqv t oe output enable to output delay read max 25 ns poll max 35 t axqx t oh output hold time from addresses, ce# or oe#, whichever occurs first min 0 ns t ehqz t df chip enable or output enable to output high-z (note 1) max 15 ns t oeh output enable hold time (note 1) read min 0 ns poll min 10 ns t aso address setup time poll min 15 ns t ash address hold time poll min 0 ns t ceph ce# high poll min 20 ns t oep oe# low poll min 25 ns t oeph oe# high poll min 20 ns t oec oe# cycle time poll min 60 ns t assb automatic sleep to standby time (note 1) ce# = v il , address stable typ 5 s max 8 s t blel t flel byte# low to ce# low min 10 ns t bhel t fhel byte# high to ce# low min 10 ns t blqv t flqv byte# low to output high-z (note 1) max 1 s t bhqv t fhqv byte# high to output delay max 1 s
document number: 002-00247 rev. *g page 76 of 105 s29gl01gt, s29gl512t note: 1. not 100% tested. table 11.4 read operation v io = 1.65v to v cc , v cc = 2.7v to 3.6v ( ? 40c to +85c) parameter description test setup speed option unit jedec std 110 t avav t rc read cycle time (note 1) 512 mb, 1 gb min 110 ns t avqv t acc address to output delay ce# = v il oe# = v il 512 mb, 1 gb max 110 ns t elqv t ce chip enable to output delay oe# = v il 512 mb, 1 gb max 110 ns t pacc page access time 512 mb, 1 gb min 25 ns t glqv t oe output enable to output delay read and poll max 35 ns t axqx t oh output hold time from addresses, ce# or oe#, whichever occurs first min 0 ns t ehqz t df chip enable or output enable to output high-z (note 1) max 20 ns t oeh output enable hold time (note 1) read min 0 ns poll min 10 ns t aso address setup poll min 15 ns t ash address hold time poll min 0 ns t ceph ce# high poll min 20 ns t oep oe# low poll min 25 ns t oeph oe# high poll min 20 ns t oec oe# cycle time poll min 60 ns t assb automatic sleep to standby time (note 1) ce# = v il , address stable typ 5 s max 8 s t blel t flel byte# low to ce# low min 10 ns t bhel t fhel byte# high to ce# low min 10 ns t blqv t flqv byte# low to output high-z (note 1) max 1 s t bhqv t fhqv byte# high to output delay max 1 s
document number: 002-00247 rev. *g page 77 of 105 s29gl01gt, s29gl512t note: 1. not 100% tested. table 11.5 read operation v io = v cc = 2.7 v to 3.6 v ( ? 40 c to +105 c) parameter description test setup speed option unit jedec std 110 t avav t rc read cycle time (note 1) 512 mb, 1 gb min 110 ns t avqv t acc address to output delay ce# = v il oe# = v il 512 mb, 1 gb max 110 ns t elqv t ce chip enable to output delay oe# = v il 512 mb, 1 gb max 110 ns t pacc page access time 512 mb, 1 gb max 15 ns t glqv t oe output enable to output delay read max 25 ns poll max 35 t axqx t oh output hold time from addresses, ce# or oe#, whichever occurs first min 0 ns t ehqz t df chip enable or output enable to output high-z (note 1) max 15 ns t oeh output enable hold time (note 1) read min 0 ns poll min 10 ns t aso address setup time poll min 15 ns t ash address hold time poll min 0 ns t ceph ce# high poll min 20 ns t oep oe# low poll min 25 ns t oeph oe# high poll min 20 ns t oec oe# cycle time poll min 60 ns t assb automatic sleep to standby time (note 1) ce# = v il , address stable typ 5 s max 8 s t blel t flel byte# low to ce# low min 10 ns t bhel t fhel byte# high to ce# low min 10 ns t blqv t flqv byte# low to output high-z (note 1) max 1 s t bhqv t fhqv byte# high to output delay max 1 s
document number: 002-00247 rev. *g page 78 of 105 s29gl01gt, s29gl512t note: 1. not 100% tested. table 11.6 read operation v io = 1.65v to v cc , v cc = 2.7v to 3.6v ( ? 40c to +105c) parameter description test setup speed option unit jedec std 120 t avav t rc read cycle time (note 1) 512 mb, 1 gb min 120 ns t avqv t acc address to output delay ce# = v il oe# = v il 512 mb, 1 gb max 120 ns t elqv t ce chip enable to output delay oe# = v il 512 mb, 1 gb max 120 ns t pacc page access time 512 mb, 1 gb max 25 ns t glqv t oe output enable to output delay read and poll max 35 ns t axqx t oh output hold time from addresses, ce# or oe#, whichever occurs first min 0 ns t ehqz t df chip enable or output enable to output high-z (note 1) max 15 ns t oeh output enable hold time (note 1) read min 0 ns poll min 10 ns t aso address setup time poll min 15 ns t ash address hold time poll min 0 ns t ceph ce# high poll min 20 ns t oep oe# low poll min 25 ns t oeph oe# high poll min 20 ns t oec oe# cycle time poll min 60 ns t assb automatic sleep to standby time (note 1) ce# = v il , address stable typ 5 s max 8 s t blel t flel byte# low to ce# low min 10 ns t bhel t fhel byte# high to ce# low min 10 ns t blqv t flqv byte# low to output high-z (note 1) max 1 s t bhqv t fhqv byte# high to output delay max 1 s
document number: 002-00247 rev. *g page 79 of 105 s29gl01gt, s29gl512t note: 1. not 100% tested. table 11.7 read operation v io = v cc = 2.7 v to 3.6 v (?40 c to +125 c) parameter description test setup speed option unit jedec std 120 t avav t rc read cycle time (note 1) ce# = v il oe# = v il 512 mb, 1 gb min 120 ns t avqv t acc address to output delay oe# = v il 512 mb, 1 gb max 120 ns t elqv t ce chip enable to output delay 512 mb, 1 gb max 120 ns t pacc page access time 512 mb, 1 gb max 15 ns t glqv t oe output enable to output delay read max 25 ns poll max 35 ns t axqx t oh output hold time from addresses, ce# or oe#, whichever occurs first min 0 ns t ehqz t df chip enable or output enable to output high-z (note 1) max 15 ns t oeh output enable hold time (note 1) read min 0 ns poll min 10 ns t aso address setup time poll min 15 ns t ash address hold time poll min 0 ns t ceph ce# high poll min 20 ns t oep oe# low poll min 25 ns t oeph oe# high poll min 20 ns t oec oe# cycle time poll min 60 ns t assb automatic sleep to standby time (note 1) ce# = v il , address stable typ 5 s max 8 s t blel t flel byte# low to ce# low min 10 ns t bhel t fhel byte# high to ce# low min 10 ns t blqv t flqv byte# low to output high-z (note 1) max 1 s t bhqv t fhqv byte# high to output delay max 1 s
document number: 002-00247 rev. *g page 80 of 105 s29gl01gt, s29gl512t note: 1. not 100% tested. table 11.8 read operation v io = 1.65 v to v cc , v cc = 2.7 v to 3.6 v (?40 c to +125 c) parameter description test setup speed option unit jedec std 130 t avav t rc read cycle time (note 1) ce# = v il oe# = v il 512 mb, 1 gb min 130 ns t avqv t acc address to output delay oe# = v il 512 mb, 1 gb max 130 ns t elqv t ce chip enable to output delay 512 mb, 1 gb max 130 ns t pacc page access time 512 mb, 1 gb max 20 ns t glqv t oe output enable to output delay read max 25 ns poll max 35 ns t axqx t oh output hold time from addresses, ce# or oe#, whichever occurs first min 0 ns t ehqz t df chip enable or output enable to output high-z (note 1) max 15 ns t oeh output enable hold time (note 1) read min 0 ns poll min 10 ns t aso address setup time poll min 15 ns t ash address hold time poll min 0 ns t ceph ce# high poll min 20 ns t oep oe# low poll min 25 ns t oeph oe# high poll min 20 ns t oec oe# cycle time poll min 60 ns t assb automatic sleep to standby time (note 1) ce# = v il , address stable typ 5 s max 8 s t blel t flel byte# low to ce# low min 10 ns t bhel t fhel byte# high to ce# low min 10 ns t blqv t flqv byte# low to output high-z (note 1) max 1 s t bhqv t fhqv byte# high to output delay max 1 s
document number: 002-00247 rev. *g page 81 of 105 s29gl01gt, s29gl512t figure 11.5 back to back read (t acc ) operation timing diagram note: 1. address are amax:a0 in word mode; amax:a-1 in byte mode, data are dq15-dq0 in word mode; dq7-dq0 in byte mode. figure 11.6 back to back read operation (t rc )timing diagram notes: 1. address are amax:a0 in word mode; amax:a-1 in byte mode, data are dq15-dq0 in word mode; dq7-dq0 in byte mode. 2. back to back operations, in which ce# remains low between accesses, requires an address change to initiate the second access. figure 11.7 page read timing diagram notes: 1. address are amax:a0 in word mode; amax:a-1 in byte mode, data are dq15-dq0 in word mode; dq7-dq0 in byte mode. 2. toggle a3:a0. in word mode; a3:a-1 in byte mode. amax-a0 ce# oe# dq15-dq0 tacc toe tce tdf tdf toh toh toh amax-a0 ce# oe# dq15-dq0 trc tacc toe tce tdf toh toh amax-a4 a3-a0 ce# oe# dq15-dq0 tacc toe tce tpacc
document number: 002-00247 rev. *g page 82 of 105 s29gl01gt, s29gl512t 11.4.2 asynchronous write operations note: 1. not 100% tested. figure 11.8 back to back write operation timing diagram note: 1. address are amax:a0 in word mode; amax:a-1 in byte mode, data are dq15-dq0 in word mode; dq7-dq0 in byte mode. table 11.9 write operations parameter description v io = 2.7v to v cc v io = 1.65v to v cc unit jedec std t avav t wc write cycle time (note 1) min 60 ns t avwl t as address setup time min 0 ns t aso address setup time to oe# low during toggle bit polling min 15 ns t wlax t ah address hold time min 45 ns t aht address hold time from ce# or oe# high during toggle bit polling min 0 ns t dvwh t ds data setup time min 30 ns t whdx t dh data hold time min 0 ns t ghwl t ghwl read recovery time before write (oe# high to we# low) min 0 ns t elwl t cs ce# setup time min 0 ns t wheh t ch ce# hold time min 0 ns t wlwh t wp we# pulse width min 25 ns t whwl t wph we# pulse width high min 20 ns t sea sector erase time-out min 50 s amax-a0 ce# oe# we# dq15-dq0 tds tdh twp tas tah twph twc tcs tch
document number: 002-00247 rev. *g page 83 of 105 s29gl01gt, s29gl512t figure 11.9 back to back (ce#vil) write operation timing diagram note: 1. address are amax:a0 in word mode; amax:a-1 in byte mode, data are dq15-dq0 in word mode; dq7-dq0 in byte mode. figure 11.10 write to read (t acc ) operation timing diagram note: 1. address are amax:a0 in word mode; amax:a-1 in byte mode, data are dq15-dq0 in word mode; dq7-dq0 in byte mode. amax-a0 ce# oe# we# dq15-dq0 tds tdh twp tas tah twph twc tcs amax-a0 ce# oe# we# dq15-dq0 tacc toe toeh tdf tdf toh toh toh tas tah tds tdh twp tcs tsr/w
document number: 002-00247 rev. *g page 84 of 105 s29gl01gt, s29gl512t figure 11.11 write to read (t ce ) operation timing diagram note: 1. address are amax:a0 in word mode; amax:a-1 in byte mode, data are dq15-dq0 in word mode; dq7-dq0 in byte mode. figure 11.12 read to write (ce# v il ) operation timing diagram note: 1. address are amax:a0 in word mode; amax:a-1 in byte mode, data are dq15-dq0 in word mode; dq7-dq0 in byte mode. amax-a0 ce# oe# we# dq15-dq0 tacc toe toeh tce tdf tdf toh toh toh tas tah tds tdh twp tcs tch tsr/w amax-a0 ce# oe# we# dq15-dq0 tas tds tah tdh tch tacc tce toe toh toh tdf twp tghwl
document number: 002-00247 rev. *g page 85 of 105 s29gl01gt, s29gl512t figure 11.13 read to write (ce# toggle) operation timing diagram note: 1. address are amax:a0 in word mode; amax:a-1 in byte mode, data are dq15-dq0 in word mode; dq7-dq0 in byte mode. notes: 1. not 100% tested. 2. upon the rising edge of we#, must wait t sr/w before switching to another address. 3. see table 5.7 on page 44 and table 5.8 on page 45 for specific values. table 11.10 erase/program operations parameter description v io = 2.7v to v cc v io = 1.65v to v cc unit jedec std t whwh1 t whwh1 write buffer program operation typ (note 3) s effective write buffer program operation per word typ (note 3) s program operation per word or page typ (note 3) s t whwh2 t whwh2 sector erase operation (note 1) typ (note 3) ms t busy erase/program valid to ry/by# delay max 80 ns t sr/w latency between read and write operations (note 2) min 10 ns t esl erase suspend latency max (note 3) s t psl program suspend latency max (note 3) s t rb ry/by# recovery time min 0 s t ppb ppb lock unlock min 80 s max 120 t dp data polling to protected sector (program) min 3 s max 20 data polling to protected sector (erase) min 3 max 100 t vhh v hh rise and fall time (note 1) min 250 ns t tor exceeded timing cleared (dq5) min 100 ns amax-a0 ce# oe# we# dq15-dq0 tacc toe tce tas tcs tds tah tdh twp tch toh toh toh tdf tdf tghwl
document number: 002-00247 rev. *g page 86 of 105 s29gl01gt, s29gl512t figure 11.14 accelerated program operation timing diagram figure 11.15 program operation timing diagram notes: 1. address are amax:a0 in word mode; amax:a-1 in byte mode, data are dq15-dq0 in word mode; dq7-dq0 in byte mode. 2. pa = program address, pd = program data, d out is the true data at the program address. acc t vhh v hh v il or v ih v il or v ih t vhh oe# we# ce# data addresses t ds t ah t dh t wp pd t whwh1 t wc t as t wph 555h pa pa read status data (last two cycles) a0h t cs status d out program command sequence (last two cycles) ry/by# t rb t busy t ch pa
document number: 002-00247 rev. *g page 87 of 105 s29gl01gt, s29gl512t figure 11.16 chip/sector erase operation timing diagram notes: 1. address are amax:a0 in word mode; amax:a-1 in byte mode, data are dq15-dq0 in word mode; dq7-dq0 in byte mode. 2. sa = sector address (for sector erase), va = valid address for reading status data. figure 11.17 data# polling timing diagram (during embedded algorithms) note: 1. va = valid address. illustration shows first status cycle afte r command sequence, last status read cycle, and array data read cycle. oe# ce# addresses we# data 2aah sa t ah t wp t wc t as t wph 555h for chip erase 10 for chip erase t ds t cs t dh t ch t whwh2 va va erase command sequence (last two cycles) read status data (last two cycles) ry/by# t rb t busy 30h in progress complete 55h we# ce# oe# high z t oe high z dq7 dq6?dq0 ry/by# t busy complement tr u e addresses va t oeh t ce t ch t oh t df va va status data complement valid data valid data t acc t rc status data tr u e
document number: 002-00247 rev. *g page 88 of 105 s29gl01gt, s29gl512t figure 11.18 toggle bit timing diagram (during embedded algorithms) note: 1. dq6 will toggle at any read address while the device is busy. dq 2 will toggle if the address is within the actively erasing s ector. figure 11.19 dq2 vs. dq6 relationship diagram note: 1. the system may use oe# or ce# to toggle dq2 and dq6. dq2 toggles only when read at an address within the erase-suspended sect or. 11.4.3 alternate ce# controlled write operations table 11.11 alternate ce# controlled write operations parameter description v io = 2.7v to v cc v io = 1.65v to v cc unit jedec std t avav t wc write cycle time (note 1) min 60 ns t avwl t as address setup time min 0 ns t aso address setup time to oe# low during toggle bit polling min 15 ns t wlax t ah address hold time min 45 ns t aht address hold time from ce# or oe# high during toggle bit polling min 0 ns t dvwh t ds data setup time min 30 ns t whdx t dh data hold time min 0 ns t ceph ce# high during toggle bit polling min 20 ns t 0eph oe# high during toggle bit polling min 20 ns t ghek t ghel read recovery time before write (oe# high to we# low) min 0 ns t wlel t ws we# setup time min 0 ns oe# ce# we# addresses t oeh t dh t aht t aso t oeph t oe valid data (first read) (second read) (stops toggling) t ceph t aht t as dq2 and dq6 valid data valid status valid status valid status ry/by# enter erase erase erase enter erase suspend program erase suspend read erase suspend read erase we# dq6 dq2 erase complete erase suspend suspend program resume embedded erasing
document number: 002-00247 rev. *g page 89 of 105 s29gl01gt, s29gl512t note: 1. not 100% tested. figure 11.20 back to back (ce#) write operation timing diagram note: 1. address are amax:a0 in word mode; amax:a-1 in byte mode, data are dq15-dq0 in word mode; dq7-dq0 in byte mode. figure 11.21 (ce#) write to read operation timing diagram note: 1. address are amax:a0 in word mode; amax:a-1 in byte mode, data are dq15-dq0 in word mode; dq7-dq0 in byte mode. t elwh t wh we# hold time min 0 ns t eleh t cp ce# pulse width min 25 ns t ehel t cph ce# pulse width high min 20 ns t sea sector erase time-out min 50 s table 11.11 alternate ce# controlled write operations (continued) parameter description v io = 2.7v to v cc v io = 1.65v to v cc unit jedec std amax-a0 ce# oe# we# dq15-dq0 tds tdh tas tah twc tcp tcph tws twh amax-a0 ce# oe# we# dq15-dq0 tacc toe tce tdf toh twc tas tah tds tdh tws twh toeh
document number: 002-00247 rev. *g page 90 of 105 s29gl01gt, s29gl512t 12. physical interface 12.1 56-pin tsop 12.1.1 connection diagram figure 12.1 56-pin standard tsop note: 1. pin 27, 28, and 30 are reserved for future use (rfu). 3 18 4 1 2 5 6 7 8 9 10 19 20 21 22 23 24 11 12 13 14 15 16 17 46 45 48 47 44 43 42 40 41 54 53 55 56 52 51 50 49 39 38 37 36 35 34 33 32 31 30 56-pin tsop 25 26 27 28 29 a15 a18 a14 a13 a12 a11 a10 a9 a8 a19 a20 we# reset# a21 wp#/acc ry/by# a17 a7 a6 a5 a23 a22 a4 a3 a2 a1 rfu rfu a24 a25 dq10 a16 byte# v ss dq15/a-1 dq7 dq14 dq6 dq2 dq9 dq1 dq8 dq13 dq5 dq12 dq4 v cc dq11 dq3 dq0 oe# v ss ce# a0 v io rfu nc for gl512t
document number: 002-00247 rev. *g page 91 of 105 s29gl01gt, s29gl512t 12.1.2 physical diagram figure 12.2 56-pin thin small outline package (tsop), 14 x 20 mm notes: 1 controlling dimensions are in millimeters (mm). (dimensioning and tolerancing conforms to ansi y14.5m-1982.) 2 pin 1 identifier for standard pin out (die up). 3 to be determined at the seating plane -c- . the seating plane is defined as the plane of contact that is made when the package leads are allowed to rest freely on a flat horizontal surface. 4 dimensions d1 and e do not include mold protrusion. allowable mold protusion is 0.15 mm per side. 5 dimension b does not include dambar protusion. allowable dambar protusion shall be 0.08 mm total in excess of b dimension at max material condition. minimum space between protrusion and an adjacent lead to be 0.07 mm. 6 these dimesions apply to the flat section of the lead between 0.10 mm and 0.25 mm from the lead tip. 7 lead coplanarity shall be within 0.10 mm as measured from the seating plane. 8 dimension "e" is measured at the centerline of the leads. 3160\38.10a mo-142 (b) ec ts 56 nom. --- --- 1.00 1.20 0.15 1.05 max. --- min. 0.95 0.20 0.23 0.17 0.22 0.27 0.17 --- 0.16 0.10 --- 0.21 0.10 20.00 20.20 19.80 14.00 14.10 13.90 0.60 0.70 0.50 -8? 0? --- 0.20 0.08 56 18.40 18.50 18.30 0.05 0.50 basic e r b1 jedec package symbol a a2 a1 d1 d c1 c b e l n o
document number: 002-00247 rev. *g page 92 of 105 s29gl01gt, s29gl512t 12.2 64-ball fbga 12.2.1 connection diagram figure 12.3 64-ball fortified ball grid array notes: 1. balls a1, a8, h1, and h8, no connect (nc). 2. balls b1, c1, d1, e1, and g1 reserved for future use (rfu). abcd efgh 8 nc a22 a23 vio vss a24 a25 nc 7 a1 3 a12 a1 4 a15 a16 dq15 / a-1 vss 6 a9 a8 a1 0 a11 dq7 dq14 dq13 dq6 5 we# reset# a21 a19 dq5 dq12 vcc dq4 4 ry/by# wp#/ acc a18 a20 dq2 dq10 dq11 dq3 3 a7 a1 7 a6 a5 dq0 dq8 dq9 dq1 2 a3 a4 a2 a1 a0 ce# oe# vss 1 nc rfu vio rfu nc top view product pinout nc for gl512t rfu rfu rfu byte#
document number: 002-00247 rev. *g page 93 of 105 s29gl01gt, s29gl512t 12.2.2 physical diagram ? lae064 figure 12.4 lae064?64-ball fortified ball grid array (fbga), 9 x 9 mm package lae 064 jedec n/a 9.00 mm x 9.00 mm package symbol min nom max note a --- --- 1.40 profile height a1 0.40 --- --- standoff a2 0.60 --- --- body thickness d 9.00 bsc. body size e 9.00 bsc. body size d1 7.00 bsc. matrix footprint e1 7.00 bsc. matrix footprint md 8 matrix size d direction me 8 matrix size e direction n 64 ball count b 0.50 0.60 0.70 ball diameter ed 1.00 bsc. ball pitch - d direction ee 1.00 bsc. ball pitch - e direction sd / se 0.50 bsc. solder ball placement none depopulated solder balls 3623 \ 16-038.12 \ 1.16.07 notes: 1. dimensioning and tolerancing per asme y14.5m-1994. 2. all dimensions are in millimeters. 3. ball position designation per jesd 95-1, spp-010 except as noted). 4. e represents the solder ball grid pitch. 5. symbol "md" is the ball row matrix size in the "d" direction. symbol "me" is the ball column matrix size in the "e" direction. n is the total number of solder balls. 6 dimension "b" is measured at the maximum ball diameter in a plane parallel to datum c. 7 sd and se are measured with respect to datums a and b and define the position of the center solder ball in the outer row. when there is an odd number of solder balls in the outer row parallel to the d or e dimension, respectively, sd or se = 0.000. when there is an even number of solder balls in the outer row, sd or se = e/2 8. not used. 9. "+" indicates the theoretical center of depopulated balls.
document number: 002-00247 rev. *g page 94 of 105 s29gl01gt, s29gl512t 12.2.3 physical diagram ? laa064 figure 12.5 laa064?64-ball fortified ball grid array (fbga) 3354 \ 16-038.12d package laa 064 jedec n/a 13.00 mm x 11.00 mm package symbol min nom max note a --- --- 1.40 profile height a1 0.40 --- --- standoff a2 0.60 --- --- body thickness d 13.00 bsc. body size e 11.00 bsc. body size d1 7.00 bsc. matrix footprint e1 7.00 bsc. matrix footprint md 8 matrix size d direction me 8 matrix size e direction n 64 ball count b 0.50 0.60 0.70 ball diameter ed 1.00 bsc. ball pitch - d direction ee 1.00 bsc. ball pitch - e direction sd / se 0.50 bsc. solder ball placement none depopulated solder balls notes: 1. dimensioning and tolerancing per asme y14.5m-1994. 2. all dimensions are in millimeters. 3. ball position designation per jesd 95-1, spp-010 (except as noted). 4. e represents the solder ball grid pitch. 5. symbol "md" is the ball row matrix size in the "d" direction. symbol "me" is the ball column matrix size in the "e" direction. n is the total number of solder balls. 6 dimension "b" is measured at the maximum ball diameter in a plane parallel to datum c. 7 sd and se are measured with respect to datums a and b and define the position of the center solder ball in the outer row. when there is an odd number of solder balls in the outer row parallel to the d or e dimension, respectively, sd or se = 0.000. when there is an even number of solder balls in the outer row, sd or se = e/2 8. not used. 9. "+" indicates the theoretical center of depopulated balls.
document number: 002-00247 rev. *g page 95 of 105 s29gl01gt, s29gl512t 12.3 56-ball fbga 12.3.1 connection diagram figure 12.6 56-ball fortified ball grid array note: 1. balls a3, b3, and g1 reserved for future use (rfu). 8 7 6 5 4 3 2 1 top view product pinout a21 a15 a16 a22 vss a24 a13 a12 rfu/a25 a14 dq7 dq15/a-1 dq14 a11 a9 a19 dq6 a10 dq12 dq13 dq5 a8 a20 a23 vio dq4 byte# we# ry/by# reset# vcc dq3 dq11 wp#/acc a18 rfu dq1 a17 dq10 dq9 dq2 rfu a5 a6 vss a4 dq0 oe# dq8 a7 a2 a3 a0 a1 rfu ce# abcd efg h 1 gb only
document number: 002-00247 rev. *g page 96 of 105 s29gl01gt, s29gl512t 12.3.2 physical diagram ? vbu 056 13. special handling instru ctions for fbga package special handling is required for flash memory products in fbga packages. flash memory devices in fbga packages may be damaged if ex posed to ultrasonic cleaning methods. the package and/or data integrity may be compromised if the package body is exposed to temperatures above 150c for prolonged periods of time. seating plane e1 7 se d1 e a c db e f g h 7 8 6 5 3 2 1 e 4 a1 corner 7 sd bottom view c c a d e c 0.10 (2x) c 0.10 b (2x) c 9 side view top view index mark a1 a a1 corner 0.10 0.08 b a c m m c 0.08 0.15 6 56 b g1055\ 16-038.25 \ 01.26.12 notes: 1. dimensioning and tolerancing methods per asme y14.5m-1994. 2. all dimensions are in millimeters. 3. ball position designation per jep95, section 4.3, spp-010. 4. e represents the solder ball grid pitch. 5. symbol "md" is the ball matrix size in the "d" direction. symbol "me" is the ball matrix size in the "e" direction. n is the total number of populated solder ball positions for matrix size md x me. 6 dimension "b" is measured at the maximum ball diameter in a plane parallel to datum c. 7 sd and se are measured with respect to datums a and b and define the position of the center solder ball in the outer row. when there is an odd number of solder balls in the outer row sd or se = 0.000. when there is an even number of solder balls in the outer row, sd or se = e/2 8. "+" indicates the theoretical center of depopulated balls. 9 a1 corner to be identified by chamfer, laser or ink mark, metallized mark indentation or other means. 10. outline and dimensions per customer requirement. package vbu 056 jedec n/a 9.00 mm x 7.00 mm nom package symbol min nom max note a --- --- 1.00 overall thickness a1 0.17 --- --- ball height d 9.00 bsc. body size e 7.00 bsc. body size d1 5.60 bsc. ball footprint e1 5.60 bsc. ball footprint md 8 row matrix size d direction me 8 row matrix size e direction n 56 total ball count b 0.35 0.40 0.45 ball diameter e 0.80 bsc. ball pitch sd / se 0.40 bsc. solder ball placement a1,a8,d4,d5,e4,e5,h1,h8 depopulated solder balls
document number: 002-00247 rev. *g page 97 of 105 s29gl01gt, s29gl512t 14. ordering information valid combinations ? standard the recommended combinations table lists configurations planned to be available in volume. the table below will be updated as new combinations are released. consult your local sales represent ative to confirm availability of specific combinations and to check on newly released combinations. notes: 1. additional speed, package, and temperature options maybe offe red in the future. check with your local sales representative fo r availability. 2. package type 0 is standard option. table 14.1 s29gl-t valid combinations for cfi version 1.3 s29gl-t valid combinations base opn speed (ns) package and temperature (note 1) model number packing type (note 2) ordering part number (yy = model number, x = packing type) s29gl01gt 100 dhi, fai, fhi, ghi, tfi 03, 04 0, 3 s29gl01gt10dhiyyx s29gl01gt10faiyyx s29gl01gt10fhiyyx s29gl01gt10ghiyyx s29gl01gt10tfiyyx 110 dhi, fai, fhi, ghi, tfi v3, v4 s29gl01gt11dhiyyx s29gl01gt11faiyyx S29GL01GT11FHIYYX s29gl01gt11ghiyyx s29gl01gt11tfiyyx 110 dhv, fhv, tfv 03, 04 s29gl01gt11dhvyyx s29gl01gt11fhvyyx s29gl01gt11tfvyyx 120 dhv, fhv, tfv v3, v4 s29gl01gt12dhvyyx s29gl01gt12fhvyyx s29gl01gt12tfvyyx 120 dhn, tfn 03, 04 s29gl01gt12dhnyyxx s29gl01gt12tfnyyxx 130 dhn, tfn v3, v4 s29gl01gt13dhnyyxx s29gl01gt13tfnyyxx s29gl512t 100 dhi, fai, fhi, ghi, tfi 03, 04 0, 3 s29gl512t10dhiyyx s29gl512t10faiyyx s29gl512t10fhiyyx s29gl512t10ghiyyx s29gl512t10tfiyyx 110 dhi, fai, fhi, ghi, tfi v3, v4 s29gl512t11dhiyyx s29gl512t11faiyyx s29gl512t11fhiyyx s29gl512t11ghiyyx s29gl512t11tfiyyx 110 dhv, fhv, tfv 03, 04 s29gl512t11dhvyyx s29gl512t11fhvyyx s29gl512t11tfvyyx 120 dhv, fhv, tfv v3, v4 s29gl512t12dhvyyx s29gl512t12fhvyyx s29gl512t12tfvyyx 120 dhn, tfn 03, 04 s29gl512t12dhnyyxx s29gl512t12tfnyyxx 130 dhn, tfn v3, v4 s29gl512t13dhnyyxx s29gl512t13tfnyyxx
document number: 002-00247 rev. *g page 98 of 105 s29gl01gt, s29gl512t table 14.2 s29gl-t valid combinations for cfi version 1.5 notes: 1. additional speed, package, and temperature options maybe offe red in the future. check with your local sales representative fo r availability. 2. package type 0 is standard option. s29gl-t valid combinations base opn speed (ns) package and temperature (note 1) model number packing type (note 2) ordering part number (yy = model number, x = packing type) s29gl01gt 100 dhi, fai, fhi, ghi, tfi 01, 02 0, 3 s29gl01gt10dhiyyx s29gl01gt10faiyyx s29gl01gt10fhiyyx s29gl01gt10ghiyyx s29gl01gt10tfiyyx 110 dhi, fai, fhi, ghi, tfi v1, v2 s29gl01gt11dhiyyx s29gl01gt11faiyyx S29GL01GT11FHIYYX s29gl01gt11ghiyyx s29gl01gt11tfiyyx 110 dhv, fhv, tfv 01, 02 s29gl01gt11dhvyyx s29gl01gt11fhvyyx s29gl01gt11tfvyyx 120 dhv, fhv, tfv v1, v2 s29gl01gt12dhvyyx s29gl01gt12fhvyyx s29gl01gt12tfvyyx 120 dhn, tfn 01, 02 s29gl01gt12dhvyyxx s29gl01gt12fhvyyxx s29gl01gt12tfvyyxx 130 dhn, tfn v1, v2 s29gl01gt13dhnyyxx s29gl01gt13tfnyyxx s29gl512t 100 dhi, fai, fhi, ghi, tfi 01, 02 0, 3 s29gl512t10dhiyyx s29gl512t10faiyyx s29gl512t10fhiyyx s29gl512t10ghiyyx s29gl512t10tfiyyx 110 dhi, fai, fhi, ghi, tfi v1, v2 s29gl512t11dhiyyx s29gl512t11faiyyx s29gl512t11fhiyyx s29gl512t11ghiyyx s29gl512t11tfiyyx 110 dhv, fhv, tfv 01, 02 s29gl512t11dhvyyx s29gl512t11fhvyyx s29gl512t11tfvyyx 120 dhv, fhv, tfv v1, v2 s29gl512t12dhvyyx s29gl512t12fhvyyx s29gl512t12tfvyyx 120 dhn, tfn 01, 02 s29gl512t12dhnyyxx s29gl512t12tfnyyxx 130 dhn, tfn v1, v2 s29gl512t13dhnyyxx s29gl512t13tfnyyxx
document number: 002-00247 rev. *g page 99 of 105 s29gl01gt, s29gl512t valid combinations ? au tomotive grade / aec-q100 the table below lists configurations that are automotive grade / aec-q100 qualified and are planned to be available in volume. the table will be updated as new combinations are released. consult your local sales representative to confirm availability of spec ific combinations and to check on newly released combinations. production part approval process (ppap) suppor t is only provided for aec-q100 grade products. products to be used in end-use applications that require iso/ts-16949 compliance must be aec-q100 grade products in combination with ppap. non?aec-q100 grade products are no t manufactured or documented in full compliance with iso/ts-16949 requirements. aec-q100 grade products are also offered without ppap suppor t for end-use applications that do not require iso/ts-16949 compliance. table 14.3 s29gl-t valid combinations for cfi version 1.3 ? automo tive grade / aec-q100 s29gl-t valid combinations ? automotive grade / aec-q100 base opn speed (ns) package and temperature model number packing type ordering part number (yy = model number, x = packing type) s29gl01gt 100 dha, fha, tfa 03, 04 0, 3 s29gl01gt10dhayyx s29gl01gt10fhayyx s29gl01gt10tfayyx 110 dha, fha, tfa v3, v4 s29gl01gt11dhayyx s29gl01gt11fhayyx s29gl01gt11tfayyx 110 dhb, fhb, tfb 03, 04 s29gl01gt11dhbyyx s29gl01gt11fhbyyx s29gl01gt11tfbyyx 120 dhb, fhb, tfb v3, v4 s29gl01gt12dhbyyx s29gl01gt12fhbyyx s29gl01gt12tfbyyx s29gl512t 100 dha, fha, tfa 03, 04 0, 3 s29gl512t10dhayyx s29gl512t10fhayyx s29gl512t10tfayyx 110 dha, fha, tfa v3, v4 s29gl512t11dhayyx s29gl512t11fhayyx s29gl512t11tfayyx 110 dhb, fhb, tfb 03, 04 s29gl512t11dhbyyx s29gl512t11fhbyyx s29gl512t11tfbyyx 120 dhb, fhb, tfb v3, v4 s29gl512t12dhbyyx s29gl512t12fhbyyx s29gl512t12tfbyyx
document number: 002-00247 rev. *g page 100 of 105 s29gl01gt, s29gl512t table 14.4 s29gl-t valid combinations for cfi version 1.5 ? automo tive grade / aec-q100 s29gl-t valid combinations ? automotive grade / aec-q100 base opn speed (ns) package and temperature model number packing type ordering part number (yy = model number, x = packing type) s29gl01gt 100, 110 dha, fha, tfa 01, 02 0, 3 s29gl01gt10dhayyx s29gl01gt10fhayyx s29gl01gt10tfayyx s29gl01gt11dhayyx s29gl01gt11fhayyx s29gl01gt11tfayyx 110 dha, fha, tfa v1, v2 s29gl01gt11dhayyx s29gl01gt11fhayyx s29gl01gt11tfayyx 110 dhb, fhb, tfb 01, 02 s29gl01gt11dhbyyx s29gl01gt11fhbyyx s29gl01gt11tfbyyx 120 dhb, fhb, tfb v1, v2 s29gl01gt12dhbyyx s29gl01gt12fhbyyx s29gl01gt12tfbyyx s29gl512t 100 dha, fha, tfa 01, 02 0, 3 s29gl512t10dhayyx s29gl512t10fhayyx s29gl512t10tfayyx 110 dha, fha, tfa v1, v2 s29gl512t11dhayyx s29gl512t11fhayyx s29gl512t11tfayyx 110 dhb, fhb, tfb 01, 02 s29gl512t11dhbyyx s29gl512t11fhbyyx s29gl512t11tfbyyx 120 dhb, fhb, tfb v1, v2 s29gl512t12dhbyyx s29gl512t12fhbyyx s29gl512t12tfbyyx
document number: 002-00247 rev. *g page 101 of 105 s29gl01gt, s29gl512t the ordering part number for the general market device is formed by a valid combination of the following: 15. other resources 15.1 cypress flash memory roadmap www.cypress.com/flash-roadmap 15.2 links to software www.cypress.com/software-and-d rivers-cypress-flash-memory 15.3 links to application notes www.cypress.com/cypressappnotes s29gl01gt 10 d h i 01 0 packing type 0 = tray 3 = 13? tape and reel model number (cfi version, v io , and v cc range) cfi version 1.3 03 = v io = v cc = 2.7 to 3.6v, highest address sector protected 04 = v io = v cc = 2.7 to 3.6v, lowest address sector protected v3 = v io = 1.65 to v cc , v cc = 2.7 to 3.6v, highest address sector protected v4 = v io = 1.65 to v cc , v cc = 2.7 to 3.6v, lowest address sector protected cfi version 1.5 01 = v io = v cc = 2.7 to 3.6v, highest address sector protected 02 = v io = v cc = 2.7 to 3.6v, lowest address sector protected v1 = v io = 1.65 to v cc , v cc = 2.7 to 3.6v, highest address sector protected v2 = v io = 1.65 to v cc , v cc = 2.7 to 3.6v, lowest address sector protected temperature range i = industrial (-40 c to +85 c) v = industrial plus (-40 c to +105 c) n = extended (-40 c to +125 c) a = automotive, aec-q100 grade 3 (-40 c to +85 c) b = automotive, aec-q100 grade 2 (-40 c to +105 c) package materials set a = not lead (pb)-free f = lead free (pb-free) h = low halogen, pb-free package type d = fortified ball-grid array package (lae064) 9 mm x 9 mm f = fortified ball-grid array package (laa064) 13 mm x 11 mm g = fortified ball-grid array package (vbu056) 9 mm x 7 mm t = thin small outline package (tsop) standard pinout speed option 10 = 100 ns random access time 11 = 110 ns random access time 12 = 120 ns random access time 13 = 130 ns random access time device number/description s29gl01gt, s29gl512t 3.0 volt core, with v io option, 1024, 512 megabit page-mode flash memory, manufactured on 45 nm mirrorbit eclipse process technology
document number: 002-00247 rev. *g page 102 of 105 s29gl01gt, s29gl512t 16. document history page document title: s29gl01gt, s29gl512t, 1 gbit (128 mbyte), 512 mbit (64 mbyte) gl-t mirrorbit ? eclipse? flash document number: 002-00247 rev. ecn no. orig. of change submission date description of change ** ? rysu 01/19/2015 initial release *a ? rysu 05/08/2015 performance summary: typical program and erase rates table: updated sector erase for ? 40 c to +85 c embedded algorithm performance table: embedded algorithm characteristics ( ? 40 c to +85 c) table: updated sector erase time, chip erase, and max single word programming time device id and common flash interf ace (id-cfi) aso map: cfi system interface string table: updated ?(sa) + 0023h? data *b ? rysu 07/29/2015 performance summary: typical progra m and erase rates table: updated sector erase for ? 40 c to +105 c embedded algorithm performance table: embedded algorithm characteristics ( ? 40 c to +105 c) table: updated sector erase time, chip erase, single word programming time, buffer programming time, effective write buffer program operation per word, and sector programming time 128 kb device id and common flash interf ace (id-cfi) aso map: cfi system interface string table: updated data for word address (sa) + 0023h and (sa) + 0024h *c 4892315 bwha 08/24/2015 updated to cypress template. *d 4951321 bwha 10/07/2015 added a note on errata in page 1. added errata. *e 5034419 crle 12/08/2015 added extended temperature range rela ted information in all instances across the document. removed note on errata in page 1. updated ordering information : updated table 14.1 : updated details in ?package and temperature? column and ?ordering part number? column. removed errata.
document number: 002-00247 rev. *g page 103 of 105 s29gl01gt, s29gl512t *f 5167972 nfb 03/09/2016 updated performance summary : replaced ?performance summary industrial plus temperature range? with ?performance summary extended temperature range? in table title. replaced ?200 a? with ?215 a? in ??40 c to +125 c? column corresponding to ?standby? operation in ?maximum current consumption? table. updated product overview : updated table 1.1 : corrected typos in ?8? column. updated description below table 1.1 (removed (a7 = 0 or a7 =1) from 7th paragraph of the section). updated data protection : updated sector protection methods : updated password protection mode : updated ppb password protection mode : updated description. updated timing specifications : updated ac characteristics : updated asynchronous read operations : added table 11.7 and table 11.8 . updated physical interface : updated 64-ball fbga : updated physical diagram ? lae064 : updated figure 12.4 (updated with the latest revision). updated ordering information : no change in part numbers. updated ordering code definitions below table 14.1 . 16. document history page (continued) document title: s29gl01gt, s29gl512t, 1 gbit (128 mbyte), 512 mbit (64 mbyte) gl-t mirrorbit ? eclipse? flash document number: 002-00247 rev. ecn no. orig. of change submission date description of change
document number: 002-00247 rev. *g page 104 of 105 s29gl01gt, s29gl512t *g 5478677 nfb 10/27/2016 updated copyright and disclaimer. updated distinctive characteristics to include ecc and automotive grade products. updated performance summary on page 2 . updated table 1.1, s29gl-t address map on page 5 . added section 2.7, ecc status aso on page 11 . added section 5.3, automatic ecc on page 21 . added section 6., data integrity on page 47 . updated table 7.1, command definitions x16 on page 48 to include ecc command set definitions. updated table 7.2, command definitions x8 on page 51 to include ecc command set definitions. updated table 7.7, cfi primary vendor-specific extended query on page 58 to differentiate between cfi 1.3 and cfi 1.5. added section 10.2, thermal resistance on page 65 . section 10.4.1, temperature ranges on page 66 : added automotive grade. ordering information on page 97 : added model numbers 03, 04, v3, v4 to denote cfi 1.3 and cfi 1.5. added package material set a to denote leaded parts. added valid combinations ? automotive grade / aec-q100 on page 99 . updated table 14.1, s29gl-t valid comb inations for cfi version 1.3 on page 97 to denote cfi 1.3. added table 14.2, s29gl-t valid combinations for cfi version 1.5 on page 98 . updated other resources on page 101 . removed data integrity information in the following tables: table 5.7, embedded algorithm characteristics (-40c to +85c) on page 44 . table 5.8, embedded algorithm characteristics (-40 c to +105 c) on page 45 . table 5.9, embedded algorithm characteristics (-40 c to +125 c) on page 46 . 16. document history page (continued) document title: s29gl01gt, s29gl512t, 1 gbit (128 mbyte), 512 mbit (64 mbyte) gl-t mirrorbit ? eclipse? flash document number: 002-00247 rev. ecn no. orig. of change submission date description of change
document number: 002-00247 rev. *g revised october 27, 2016 page 105 of 105 ? cypress semiconductor corporation, 2015-2016. this document is the property of cypress semiconductor corporation and its subs idiaries, including spansion llc (?cypress?). this document, including any software or firmware included or referenced in this document (?software?), is owned by cypress under the intellec tual property laws and treaties of the united states and other countries worldwide. cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragr aph, grant any license under its patents, copyrights, trademarks, or other intellectual property rights. if the software is not accompanied by a license agreement and you do not otherwise have a written agreement with cypress governing the use of the software, then cypress hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the software (a) for software provided in source code form, to modify and reproduce the software solely for use with cypress hardware products, only internally within your organization, and (b) to distribute the software in binary code form externally to end users (either directly or indirectly through resellers and distributors), solely for use on cypress hardware product units, and (2) u nder those claims of cypress's patents that are infringed by the software (as provided by cypress, unmodified) to make, use, distribute, and import the software solely for use with cypress hardware product s. any other use, reproduction, modi fication, translation, or compilation of the software is prohibited. to the extent permitted by applicable law, cypress makes no warranty of any kind, express or implied, with regard to this docum ent or any software or accompanying hardware, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. to the extent permitted by applicable law, cypress reserves the right to make changes to this document without further notice. cypress does n ot assume any liability arising out of the application or use of any product or circuit described in this document. any information provided in this document, including any sample design informati on or programming code, is provided only for reference purposes. it is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any appli cation made of this information and any resulting product. cypress products are not designed, intended, or authorized fo r use as critical components in systems de signed or intended for the operation of w eapons, weapons systems, nuclear inst allations, life-support devices or systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazar dous substances management, or other uses where the failure of the device or system could cause personal injury, death, or property damage (?unintended uses?). a critical component is any compon ent of a device or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affe ct its safety or effectiveness. cypress is not liable, in whol e or in part, and you shall and hereby do release cypress from any claim, damage, or other liability arising from or related to all uninte nded uses of cypress products. you shall indemnify and hold cyp ress harmless from and against all claims, costs, damages, and other liabilities, including claims for personal inju ry or death, arising from or related to any unintended uses of cypress products. cypress, the cypress logo, spansion, the spansion logo, and combinations thereof, wiced, psoc, capsense, ez-usb, f-ram, and tra veo are trademarks or registered trademarks of cypress in the united states and other countries. for a more complete list of cypress trademarks, visit cypress.com. other names and brand s may be claimed as property of their respective owners. s29gl01gt, s29gl512t sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products arm ? cortex ? microcontrollers cypress.com/arm automotive cypress.com/automotive clocks & buffers cypress.com/clocks interface cypress.com/interface internet of things cypress.com/iot lighting & power control cypress.com/powerpsoc memory cypress.com/memory psoc cypress.com/psoc touch sensing cypress.com/touch usb controllers cypress.com/usb wireless/rf cypress.com/wireless psoc ? solutions psoc 1 | psoc 3 | psoc 4 | psoc 5lp cypress developer community forums | projects | video | blogs | training | components technical support cypress.com/support

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